Table 3-2 Ram Configuration Bit Settings For The Dsp56305 - Motorola DSP56305 User Manual

3.2 RAM CONFIGURATION
The DSP56305 contains 12.25 K of RAM, divided by default into:
• Program RAM (6.5 K)
• X data RAM (3.75 K)
• Y data RAM (2.0 K)
RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the
Memory Select (MS) of the OMR.

Table 3-2 RAM Configuration Bit Settings for the DSP56305

Bit
Abbreviation
CE
MS
Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-8.
The MS bit may not be changed when CE is set. The Instruction Cache
Note:
occupies the top 1 K of what would otherwise be Program RAM, and to switch
memory into or out of Program RAM when the cache is enabled will cause
conflicts. To change the MS bit when CE is set:
1. clear CE
2. change MS
3. set CE
MOTOROLA
Bit
Bit Name
Location
Cache SR 19
Enable
Memory OMR 7
Switch
DSP56305 User's Manual
Cleared = 0 Effect
(Default)
Cache Disabled
Program RAM 6.5 K
X data RAM 3.75 K
Y data RAM 2.0 K
Memory Configuration
RAM Configuration
Set = 1 Effect
Cache Enabled
1 K
Program RAM 7.5 K
X data RAM 2.75 K
Y data RAM 2.0 K
3-7