Motorola DSP56305 User Manual page 70

Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Table 2-8 External Bus Control Signals (Continued)
Signal
Type
Name
TA Input
2-12
State During
Reset, Wait,
or Stop
Ignored Transfer Acknowledge—If the DSP56305 is the bus
Input master and there is no external bus activity, or if the
DSP56305 is not the bus master, TA is ignored. TA is a
Data Transfer Acknowledge (DTACK) function that
can extend an external bus cycle indefinitely. Any
number of wait states (1, 2,..., infinity) may be added to
the wait states inserted by the Bus Control Register
(BCR) by keeping TA deasserted. In typical operation,
TA is deasserted at the start of a bus cycle, is asserted
to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus
cycle completes one clock period after TA is asserted
synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the BCR, whichever
is longer. The BCR can be used to set the minimum
number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be
programmed to at least one wait state. A zero wait
state access can not be extended by TA deassertion,
otherwise improper operation may result. TA can
operate synchronously or asynchronously depending
on the setting of the TAS bit in the Operating Mode
Register (OMR).
TA functionality may not be used while performing
DRAM type accesses, otherwise improper operation
may result.
DSP56305 User's Manual
Signal Description
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