Table 13-7 Memory Modules Usage And Access; Chip Description; Memory Description - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR

Chip Description

13.6 CHIP DESCRIPTION
This section describes the memory, interrupts, DMA source, and soft decision formats of
the VCOP of the DSP56305.
13.6.1

Memory description

Memory
Memory
1
Size
Module
32 x 16
2
VP
2 64 x 16
WED
Reserved 7 x 16
Path 64 x 22
Metric
DELAY 45 x 16
Trellis 64 x 36
OUTPUT 1023 x 1
BUFF or 63 x 16
Note: 1. There is no continuity in accessing different memory sections. Therefore, whenever a new
memory section is to be accessed, VBER should be explicitly assigned a starting address of
that memory section.
2. WED and VP RAMs are implemented by a common physical RAM, allocated for either WED
(at decoding) or as VP (at equalization).
13-30

Table 13-7 Memory modules usage and access

Operation Modes Using the
Address
(VBER)
Equaliz-
ation
$0 – $1F yes
$0 – $3F -
$40 – $46 reserved
$80 – $BF yes
$C0 – $EC yes
yes
yes
DSP56305 User's Manual
Module
Decoding Encoding
- -
yes, if -
enabled
reserved reserved
yes -.
yes -
yes
yes yes
Accessed By
VMEM Register
VMEM Register
VMEM Register
VMEM Register
VMEM Register
Internal logic only
VDOR
MOTOROLA