Table of Contents
Advertisement
6.5.2.11
Master Access Counter Enable (MACE) Bit 18
The MACE bit is used to enable the master access counter.
If MACE is set, the master access counter is enabled and the HI32 as the active PCI
master (HM=$1) will terminate the current PCI transaction when the burst length
counter reaches the terminal count. This is called a limited length burst. The initial value
is loaded from the Burst Length bits (Bl[5:0]).
If MACE is cleared, the counter is disabled, and the burst length of transactions initiated
by the HI32 are unlimited.
The DSP56300 core can terminate a transaction initiated by the HI32 by writing one to
the MTT bit in the DPCR.
MACE is ignored when the HI32 is not in the PCI mode (HM≠$1).
The value of MACE may be changed only if MARQ = 1, or HACT = 0.
Hardware and software resets clear MACE.
6.5.2.12
Master Wait State Disable (MWSD) Bit 19
The MWSD bit is used to disable PCI wait states (inserted by negating HIRDY), during a
data phase.
If MWSD is cleared, the HI32 as the active PCI master (HM=$1) will insert wait states to
extend the current data phase if it cannot guarantee the completion of the next data
phase. This is a consequence of the PCI requirement that the Initiator Ready (HINTA)
signal be asserted by the master at the end of every data phase.The HI32 will assert
HIRDY and complete the current data phase if:
• it can complete the next data phase, or
• it has determined to terminate the transaction due to time-out or completion.
If MWSD is set, the HI32, as the active PCI master (HM=$1) will not insert wait states. If
it cannot guarantee the completion of the next data phase, the HI32 will complete the
current data phase and terminate the transaction.
MWSD is ignored when the HI32 is not in the PCI mode (HM≠$1).
The value of MWSD may be changed only when HACT = 0.
Hardware and software resets clear MWSD.
MOTOROLA
DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
6-25
Advertisement
Chapters
Table of Contents
