If Fc = $3:; Dsp Pci Address Register (Dpar) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.3.5.3

If FC = $3:

The three most significant PCI data bytes from the HAD31-HAD8 signals are transferred
to the DRXR to be read by the DSP56300 core.
To assure proper operation: FC1-FC0 may be changed only if both the host-to-DSP and
the DSP-to-host master data paths are empty. In addition, switching between 32-bit data
modes and non-32-bit data modes may be done only in the personal software reset state
(HM = $0 and HACT = 0).
FC1-FC0 are ignored when not in the PCI mode (HMπ$1).
The DPMC bits are ignored when not in the PCI mode (HMπ$1).
Hardware and software resets clear FC1-FC0.
6.5.4

DSP PCI Address Register (DPAR)

11 10 9
AR11 AR10 AR9
23 22 21
BE3 BE2 BE1
Bit
15-0
19-16 C[3:0]
23-20 BE{3:0]
The DPAR is a 24-bit read/write register used by the DSP56300 core to generate the two
least significant bytes of the 32-bit PCI transaction address, the PCI bus command, and
the PCI bus byte enables. The DPAR cannot be accessed by the host processor. The two
most significant bytes of the PCI transaction address are located in the DSP PCI master
control register (DPMC, see Section 6.5.3).
6-32
8 7 6
AR8 AR7 AR6
20 19 18
BE0 C3 C2
Name
AR[15:0] DSP PCI Transaction Address (Low)
PCI Bus Command
PCI Byte Enables
DSP56305 User's Manual
5 4 3
AR5 AR4 AR3
17 16 15
C1 C0 AR15
Function
2 1 0
AR2 AR1 AR0
14 13 12
AR14 AR13 AR12
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