Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled - Motorola DSP56305 User Manual

24-bit digital signal processor
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Program
$FFFF
$1A00
$1600
Internal Program
$0000
Program
RAM: 5.5 K
$0000–$15FF
Note:
This column gives the maximum memory addressable in the memory space.

Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled

MOTOROLA
SC = 1, MS = 0, CE = 1
External
$FFFF
$FF80
Instruction
Cache
1 K
$0F00
RAM
5.5 K
$0000
Memory Configuration
X Data
RAM: 3.75 K
$0000–$0EFF
DSP56305 User's Manual
Memory Configuration
X Data
Internal I/O
$FFFF
128 words
$FFC0
External
$FF80
$0800
Internal
X data RAM
3.75 K
$0000
Y Data
RAM: 2 K
$0000–$07FF
$1600–$19FF
Memory Maps
Y Data
External I/O
128 words
Internal I/O
64 words
External
Internal
Y data RAM
2 K
Max.
Cache
*
Mem.
1 K
64 K
3-17

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