Table 6-9 Pci Bus Commands Supported By The Hi32 As Pci Master; Pci Byte Enables (Be3-Be0) Bits 15-12 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model

Table 6-9 PCI Bus Commands Supported by the HI32 as PCI Master

Illegal C3-C0 values are not supported by the HI32 and should not be used.
Hardware and software resets clear C3-C0.
6.5.4.2

PCI Byte Enables (BE3-BE0) Bits 15-12

The BE3-BE0 determine which byte lanes carry meaningful data when in the PCI mode
(HM=$1) and the HI32 is a PCI master. BE3 applies to byte 3, and BE0 to byte 0. Byte
enables are driven to HC3/HBE3-HC0/HBE0 signals during the PCI data phases.
The HI32, as master, drives all the HRXM data to the HAD31-HAD0 signals during write
transactions, and writes the HAD31-HAD0 signals to the HTXR (in accordance with the
FC1-FC0 bits) in read transactions, regardless of the BE3-BE0 value.
Hardware and software resets clear BE3-BE0.
6-34
C3-C0
0000 illegal
0001 illegal
0010 I/O read
0011 I/O Write
0100 illegal
0101 illegal
0110 Memory Read
0111 Memory Write
1000 illegal
1001 illegal
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 illegal
1110 Memory Read Line
1111 illegal
DSP56305 User's Manual
Command Type
MOTOROLA