Motorola DSP56305 User Manual page 282

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.2.10 Clock Polarity (CKP) CRB Bit 11
The CKP bit controls on which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising
edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If
CKP is set, the data and the frame sync are clocked out on the falling edge of the transmit
bit clock and latched in on the rising edge of the receive bit clock.
Either a hardware reset signal or a software reset instruction will clear CKP.
7.4.2.11 Synchronous /Asynchronous (SYN) CRB Bit 12
SYN controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other (see Figure 7-17). When
SYN is cleared, the ESSI is in Asynchronous mode, and separate clock and frame sync
signals are used for the transmit and receive sections. When SYN is set, the ESSI is in
Synchronous mode and the transmit and receive sections use common clock and frame
sync signals. Only in the Synchronous mode can more than one transmitter can be
enabled.
Either a hardware reset signal or a software reset instruction clears SYN.
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