Interrupt Priority Levels - Motorola DSP56305 User Manual

Interrupt
Starting
Address
VBA:$7A
VBA:$7C
VBA:$7E
VBA:$80
VBA:$82
VBA:$84
VBA:$86
VBA:$88
VBA:$8A
VBA:$8C
VBA:$8E
VBA:$90
VBA:$92
VBA:$94
VBA:$96
VBA:$98
:
VBA:$FE
Note: Any Interrupt starting address (including reserved addresses) may be used for Host NMI (IPL = 3)
and for Host command interrupt (IPL = 0–2).
4.5.2

Interrupt Priority Levels

The DSP56305 has a four level interrupt priority structure. Each interrupt has two
Interrupt Priority Level bits (IPL[1:0]) that determine its interrupt priority level. Level 0
is the lowest priority level. Level 3 is the highest level priority and is non-maskable.
Table 4-3 defines the IPL bits.
MOTOROLA
Interrupt
Priority
Level
Range
0–2 FCOP Data Output Buffer Full
0–2 Reserved
0–2 Reserved
0–2 VCOP Data In Request
0–2 VCOP Output Buffer Full
0–2 VCOP Data Out Request
0–2 VCOP Processing Done
0–2 VCOP Operation Complete
0–2 Reserved
0–2 Reserved
0–2 Reserved
0–2 CCOP Input FIFO Empty
0–2 CCOP Output FIFO Not Empty
0–2 CCOP Cipher Processing Done
0–2 CCOP Parity Code Processing Done
0–2 Reserved
: :
0–2 Reserved
DSP56305 User's Manual
Core Configuration
Interrupt Sources and Priorities
Interrupt Source
4-15