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Serial Communication Interface (SCI)
SCI Programming Model
When odd parity is selected, the transmitter counts the number of 1s in the data word. If
the total is not an odd number, the parity bit is set, thus producing an odd number. If the
receiver counts an even number of 1s, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line or an error in transmission has occurred.
The word select bits are cleared by hardware and software reset.
8.3.1.2
SCI Shift Direction (SSFTD) SCR Bit 3
The SSFTD bit determines the order in which the SCI Data Shift Registers shift data in or
out: MSB first when set, LSB first when cleared. The parity and data type bits do not
change their position in the frame, and remain adjacent to the stop bit. SSFTD is cleared
by hardware and software reset.
8.3.1.3
Send Break (SBK) SCR Bit 4
A break is an all-zero word frame—a start bit 0, characters of all 0s (including any
parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is
set and then cleared, the transmitter completes transmission of the current frame, sends
ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK
remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with
no stop bit). At the completion of the break code, the transmitter sends at least one high
(set) bit before transmitting any data to guarantee recognition of a valid start bit. Break
can be used to signal an unusual condition, message, etc. by forcing a frame error, which
is caused by a missing stop bit. Hardware and software reset clear SBK.
8.3.1.4
Wakeup Mode Select (WAKE) SCR Bit 5
When WAKE is cleared, the Wakeup On Idle Line mode is selected. In the Wakeup On
Idle Line mode, the SCI receiver is re-enabled by an idle string of at least ten or eleven
(depending on WDS mode) consecutive 1s. The transmitter's software must provide this
idle string between consecutive messages. The idle string cannot occur within a valid
message because each word frame contains a start bit that is 0.
When WAKE is set, the Wakeup On Address Bit mode is selected. In the Wakeup On
Address Bit mode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit
received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit
Multidrop mode; the eighth data bit is the address bit in the 10-bit Asynchronous and
11-bit Asynchronous with parity modes. Thus, the received character is an address that
has to be processed by all sleeping processors—that is, each processor has to compare
the received character with its own address and decide whether to receive or ignore all
following characters. WAKE is cleared by hardware and software reset.
8-10
DSP56305 User's Manual
MOTOROLA
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