Sci Receive Registers (Srx); Sci Transmit Registers - Motorola DSP56305 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
8.3.4.1

SCI Receive Registers (SRX)

Data bits received on the RXD signal are shifted into the SCI Receive Shift Register.
When a complete word has been received, the data portion of the word is transferred to
the byte-wide SRX. This process converts the serial data to parallel data and provides
double-buffering. Double-buffering provides flexibility to the programmer and
increased throughput since the programmer can save (and process) the previous word
while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read,
the contents of the SRX are placed in the low byte of the data bus and the remaining bits
on the data bus are read as 0s. Similarly, when SRXM is read, the contents of SRX are
placed in the middle byte of the bus, and when SRXH is read, the contents of SRX are
placed in the high byte with the remaining bits are read as 0s. Mapping SRX as described
allows three bytes to be efficiently packed into one 24-bit word by ORing three data
bytes read from the three addresses.
The length and format of the serial word are defined by the WDS0, WDS1, and WDS2
control bits in the SCR. The clock source is defined by the Receive Clock Mode (RCM)
select bit in the SCR.
In the Synchronous mode, the start bit, the eight data bits, the address/data indicator bit
and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB
first if SSFTD is cleared, and MSB first if SSFTD is set. In Synchronous mode, the
synchronization is provided by gating the clock.
In either Synchronous or Asynchronous modes, when a complete word has been clocked
in, the contents of the Shift Register can be transferred to the SRX and the flags: RDRF,
FE, PE, and OR are changed appropriately. Because the operation of the Receive Shift
Register is transparent to the DSP, the contents of this register are not directly accessible
to the programmer.
8.3.4.2

SCI Transmit Registers

The Transmit Data Register is a one byte-wide register mapped into four addresses as
STXL, STXM, STXH, and STXA. In the Asynchronous mode, when data is to be
transmitted, STXL, STXM, and STXH are used. When STXL is written, the low byte on
the data bus is transferred to the STX. When STXM is written, the middle byte is
transferred to the STX. When STXH is written, the high byte is transferred to the STX.
This structure makes it easy for the programmer to unpack the bytes in a 24-bit word for
transmission. STXA should be written in the 11-bit Asynchronous Multidrop mode
when the data is an address and it is desired that the ninth bit (the address bit) be set.
When STXA is written, the data from the low byte on the data bus is stored in it. The
address data bit is cleared in the 11-bit Asynchronous Multidrop mode when any of
MOTOROLA DSP56305 User's Manual 8-21