Table 10-5 Core Status Bits Description; Software Debug Occurrence (Swo) Bit 2; Memory Breakpoint Occurrence (Mbo) Bit 3; Trace Occurrence (To) Bit 4 - Motorola DSP56305 User Manual

10.4.3.3

Software Debug Occurrence (SWO) Bit 2

The Software Debug Occurrence (SWO) bit is a read-only status bit that is set when the
Debug mode of operation is entered because of the execution of the DEBUG or
DEBUGcc instruction with condition true. This bit is cleared when leaving the Debug
mode.
10.4.3.4

Memory Breakpoint Occurrence (MBO) Bit 3

The Memory Breakpoint Occurrence (MBO) bit is a read-only status bit that is set when
the Debug mode of operation is entered because a memory breakpoint has been
encountered. This bit is cleared when leaving the Debug mode.
10.4.3.5

Trace Occurrence (TO) Bit 4

The Trace Occurrence (TO) bit is a read-only status bit that is set when the Debug mode
of operation is entered when the Trace Counter is zero while Trace mode is enabled. This
bit is cleared when leaving the Debug mode.
10.4.3.6

Reserved OCSR Bit 5

Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future
compatibility.
10.4.3.7

Core Status (OS0, OS1) Bits 6-7

The Core Status (OS0, OS1) bits are read-only status bits that provide core status
information. By examining the status bits, the user can determine whether the chip has
entered the Debug mode. Examining SWO, MBO, and TO identifies the cause of entering
the Debug mode. The user can also examine these bits and determine the cause why the
chip has not entered the Debug mode after debug event assertion (DE) or as a result of
the execution of the JTAG DEBUG REQUEST instruction (core waiting for the bus, STOP
or WAIT instruction, etc.). These bits are also reflected in the JTAG instruction shift
register, which allows the polling of the core status information at the JTAG level. This is
useful when the DSP56300 core executes the STOP instruction (and therefore there are
no clocks) to allow the reading of OSCR. See Table 10-5 for the definition of the
OS0–OS1 bits.
OS1
0
0
1
1
MOTOROLA

Table 10-5 Core Status Bits Description

OS0
0 DSP56300 core is executing instructions
1 DSP56300 core is in Wait or Stop
0 DSP56300 core is waiting for bus
1 DSP56300 core is in Debug mode
DSP56305 User's Manual
On-Chip Emulation Module
Description
OnCE Controller
10-9