Table 13-2 Code Rate Definition; Table 13-3 Trellis States; Code Rate (Rate[1:0])—Vcra Bits 8–9; Constraint Length (Cnst[1:0])—Vcra Bit 12–13 - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR
Programming Model
13.5.3.7 Code Rate (RATE[1:0])—VCRA Bits 8–9
The Code Rate bits (RATE[1:0]) define the convolutional code rate for both decoding and
encoding (see Table 13-2). The Code Rate bits are ignored in other modes.
13.5.3.8 Constraint Length (CNST[1:0])—VCRA Bit 12–13
The Constraint Length bits (CNST[1:0]) define the number of states in the trellis
diagram. The bit settings defining constraint length and number of trellis states are given
in Table 13-3.
CNST[1:0]
00
01
10
11
13.5.3.9 VCRA Reserved—VCRA Bits 6–7, 10–11, 14–15
These bits are reserved and should be written with zero.
13-20

Table 13-2 Code Rate Definition

RATE[1:0] RATE
00 1/2
01 1/3
10 1/4
11 1/6
Note: 1. Size required for decoding each symbol-bit
represented in a soft decision format

Table 13-3 Trellis States

Number of trellis states
8
16
32
64
DSP56305 User's Manual
1
Symbol Size In Bits
2
3
4
6
Constraint length
4
5
6
7
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