Motorola DSP56305 User Manual page 178

24-bit digital signal processor
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HOST INTERFACE (HI32)
DSP SIDE Programming Model
Table 6-8 HI32 (PCI Master) Data Transfer Formats
DSP to PCI Host Data Transfer
FC1
FC0
0
1
The three least significant HRXM bytes are output
right aligned and zero extended.
HI32
1
0
The three least significant HRXM bytes are output
right aligned and sign extended.
HI32
1
1
The three least significant HRXM bytes are output left
aligned and zero filled.
HI32
6-30
Format
GDB/MDDB
DTXM
HRXM
HDTFC
$0
PCI bus
$0
GDB/MDDB
DTXM
HRXM
HDTFC
S
PCI bus
S
GDB/MDDB
DTXM
HRXM
HDTFC
$0
PCI bus
$0
DSP56305 User's Manual
PCI Host to DSP Data Transfer
Format
The three least significant PCI data bytes are written
to the HTXR.
HI32
X
The three least significant PCI data bytes are written
to the HTXR.
HI32
X
The three most significant PCI data bytes are written
to the HTXR.
HI32
X
GDB/MDDB
DRXR
HTXR
HDTFC
PCI bus
GDB/MDDB
DRXR
HTXR
HDTFC
PCI bus
GDB/MDDB
DRXR
HTXR
HDTFC
PCI bus
MOTOROLA

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