Motorola DSP56009 Manuals

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Motorola DSP56009 User Manual

Motorola DSP56009 User Manual (286 pages)

24-Bit Digital Signal Processor  
Brand: Motorola | Category: Signal Processors | Size: 1.21 MB
Table of contents
Table Of Contents4................................................................................................................................................................
Section 1 Overview19................................................................................................................................................................
Introduction21................................................................................................................................................................
Manual Organization22................................................................................................................................................................
Manual Conventions23................................................................................................................................................................
Dsp56009 Features24................................................................................................................................................................
Dsp56009 Architectural Overview26................................................................................................................................................................
Figure 1-1 Dsp56009 Block Diagram27................................................................................................................................................................
Memory And Peripheral Modules28................................................................................................................................................................
Data Arithmetic And Logic Unit (alu)29................................................................................................................................................................
Program Control Unit30................................................................................................................................................................
On-chip Emulation (once) Port31................................................................................................................................................................
X Data Memory33................................................................................................................................................................
External Memory34................................................................................................................................................................
External Memory Interface36................................................................................................................................................................
Serial Audio Interface (sai)37................................................................................................................................................................
Section 2 Signal Descriptions39................................................................................................................................................................
Signal Groupings41................................................................................................................................................................
Figure 2-1 Dsp56009 Signals42................................................................................................................................................................
Power43................................................................................................................................................................
Clock And Pll Signals44................................................................................................................................................................
External Memory Interface (emi)45................................................................................................................................................................
Table 2-6 Emi Operating States47................................................................................................................................................................
Interrupt And Mode Control48................................................................................................................................................................
Serial Host Interface (shi)52................................................................................................................................................................
Sai Transmitter Section58................................................................................................................................................................
General Purpose I/o59................................................................................................................................................................
Table 2-12 On-chip Emulation Port Signals60................................................................................................................................................................
And Interrupts65................................................................................................................................................................
X Data Rom68................................................................................................................................................................
Reserved Memory Spaces69................................................................................................................................................................
Figure 3-1 Memory Maps For Pea = 0, Peb = 070................................................................................................................................................................
Figure 3-3 Memory Maps For Pea = 0, Peb = 171................................................................................................................................................................
Dynamic Switching Of Memory Configurations72................................................................................................................................................................
Internal I/o Memory Map73................................................................................................................................................................
Table 3-2 Internal I/o Memory Map74................................................................................................................................................................
Operating Mode Register (omr)75................................................................................................................................................................
Program Ram Enable B (peb)—bit 376................................................................................................................................................................
Table 3-3 Operating Modes77................................................................................................................................................................
Interrupt Priority Register78................................................................................................................................................................
Table 3-4 Interrupt Priorities79................................................................................................................................................................
Table 3-5 Interrupt Vectors80................................................................................................................................................................
Phase Lock Loop (pll) Configuration82................................................................................................................................................................
Hardware Reset Operation83................................................................................................................................................................
Section 4 External Memory Interface85................................................................................................................................................................
Emi Features88................................................................................................................................................................
Emi Programming Model89................................................................................................................................................................
Figure 4-1 Emi Registers90................................................................................................................................................................
Emi Base Address Registers (ebar0 And Ebar1)91................................................................................................................................................................
Emi Offset Register (eor)92................................................................................................................................................................
Emi Data Write Registers (edwr)93................................................................................................................................................................
Emi Control/status Register (ecsr)94................................................................................................................................................................
Emi Word Length (ewl[2:0])—bits 16,2, And 195................................................................................................................................................................
Emi Addressing Mode (eam[3:0])—bits 6–396................................................................................................................................................................
Table 4-6 Emi Maximum Sram Size97................................................................................................................................................................
Table 4-7 Emi Maximum Dram Size (relative Addressing)98................................................................................................................................................................
Table 4-8 Emi Maximum Dram Size (absolute Addressing)99................................................................................................................................................................
Emi Increment Ebar After Read (einr)—bit 7100................................................................................................................................................................
Emi Interrupt Select (eis[1:0])—bits 9–10101................................................................................................................................................................
Emi Data Write Register Empty (edwe)—bit 12102................................................................................................................................................................
Emi Busy (ebsy)—bit 15103................................................................................................................................................................
Estm[3:0])— Bits 19–22104................................................................................................................................................................
Emi Enable (eme)—bit 23105................................................................................................................................................................
Emi Refresh Clock Divider (ecd[7:0])—bits 0–7106................................................................................................................................................................
Ercr Refresh Enable (eref)—bit 23107................................................................................................................................................................
Sram Absolute Addressing108................................................................................................................................................................
Sram Relative Addressing109................................................................................................................................................................
Table 4-13 Word Address To Physical Address Mapping For Sram110................................................................................................................................................................
Dram Relative Addressing111................................................................................................................................................................
Table 4-14 Word-address-to-physical-address Mapping For Dram112................................................................................................................................................................
Table 4-15 Address Generation For Dram Relative Addressing113................................................................................................................................................................
Dram Absolute Addressing114................................................................................................................................................................
Dram Refresh115................................................................................................................................................................
Consideration116................................................................................................................................................................
Using The Internal Refresh Timer117................................................................................................................................................................
Off Line" Refresh118................................................................................................................................................................
Dram Refresh Timing119................................................................................................................................................................
Ecd[7:0]120................................................................................................................................................................
Figure 4-6 Timing Diagram Of A Dram Refresh Cycle (fast)121................................................................................................................................................................
Emi Operating Considerations122................................................................................................................................................................
Figure 4-8 Emi Pipeline123................................................................................................................................................................
Read Data Transfer124................................................................................................................................................................
Write-data Transfer127................................................................................................................................................................
Emi Operation During Stop129................................................................................................................................................................
Data-delay Structure130................................................................................................................................................................
Emi-to-memory Connection132................................................................................................................................................................
Figure 4-11 Sram For Data Delay Buffers And For Bootstrap133................................................................................................................................................................
Emi Timing134................................................................................................................................................................
Timing Diagrams For Dram Addressing Modes135................................................................................................................................................................
Fast Timing Mode136................................................................................................................................................................
Figure 4-14 Fast Read Or Write Dram Access Timing—2137................................................................................................................................................................
Figure 4-15 Fast Read Or Write Dram Access Timing—3138................................................................................................................................................................
Figure 4-16 Fast Read Or Write Dram Access Timing—4139................................................................................................................................................................
Figure 4-17 Fast Read Or Write Dram Access Timing—5140................................................................................................................................................................
Figure 4-18 Fast Read Or Write Dram Access Timing—6141................................................................................................................................................................
Slow Timing Mode142................................................................................................................................................................
Figure 4-20 Slow Read Or Write Dram Access Timing—2143................................................................................................................................................................
Figure 4-21 Slow Read Or Write Dram Access Timing—3144................................................................................................................................................................
Figure 4-22 Slow Read Or Write Dram Access Timing—4145................................................................................................................................................................
Figure 4-23 Slow Read Or Write Dram Access Timing—5146................................................................................................................................................................
Figure 4-24 Slow Read Or Write Dram Access Timing—6147................................................................................................................................................................
Timing Diagrams For Sram Addressing Modes148................................................................................................................................................................
Section 5 Serial Host Interface149................................................................................................................................................................
Serial Host Interface Internal Architecture152................................................................................................................................................................
Shi Clock Generator153................................................................................................................................................................
Table 5-1 Shi Interrupt Vectors155................................................................................................................................................................
Shi Input/output Shift Register (iosr)—host Side156................................................................................................................................................................
Shi Host Receive Data Fifo (hrx)—dsp Side157................................................................................................................................................................
Cpha And Cpol)—bits 1–0158................................................................................................................................................................
Hckr Prescaler Rate Select (hrs)—bit 2159................................................................................................................................................................
Hdm[5:0])—bits 8–3160................................................................................................................................................................
Shi Control/status Register (hcsr)—dsp Side161................................................................................................................................................................
Hm[1:0])—bits 3–2162................................................................................................................................................................
Hrqe[1:0])—bits 8–7163................................................................................................................................................................
Hcsr Bus-error Interrupt Enable (hbie)—bit 10164................................................................................................................................................................
Htue)—bit 14165................................................................................................................................................................
Host Receive Fifo Not Empty (hrne)—bit 17166................................................................................................................................................................
Hcsr Host Busy (hbusy)—bit 22167................................................................................................................................................................
Overview168................................................................................................................................................................
Shi Programming Considerations171................................................................................................................................................................
Spi Slave Mode172................................................................................................................................................................
Spi Master Mode173................................................................................................................................................................
Shi Operation During Stop179................................................................................................................................................................
Section 6 Serial Audio Interface181................................................................................................................................................................
Serial Audio Interface Internal Architecture184................................................................................................................................................................
Receive Section Overview185................................................................................................................................................................
Sai Transmit Section Overview186................................................................................................................................................................
Figure 6-3 Sai Transmit Section Block Diagram187................................................................................................................................................................
Serial Audio Interface Programming Model188................................................................................................................................................................
Baud Rate Control Register (brc)189................................................................................................................................................................
Prescale Modulus Select (pm[7:0])—bits 7–0190................................................................................................................................................................
Rcs Receiver 1 Enable (r1en)—bit 1191................................................................................................................................................................
Rcs Receiver Data Shift Direction (rdir)—bit 6192................................................................................................................................................................
Rcs Receiver Clock Polarity (rckp)—bit 8193................................................................................................................................................................
Rdwt)—bit 10194................................................................................................................................................................
Rcs Receiver Interrupt Enable (rxie)—bit 11195................................................................................................................................................................
Rcs Receiver Left Data Full (rldf)—bit 14196................................................................................................................................................................
Sai Receive Data Registers (rx0 And Rx1)197................................................................................................................................................................
Tcs Transmitter 2 Enable (t2en)—bit 2198................................................................................................................................................................
Tcs Transmitter Left Right Selection (tlrs)—bit 7199................................................................................................................................................................
Tcs Transmitter Relative Timing (trel)—bit 9200................................................................................................................................................................
Tcs Transmitter Interrupt Enable (txie)—bit 11201................................................................................................................................................................
Tcs Transmitter Interrupt Location (txil)—bit 12202................................................................................................................................................................
Tcs Transmitter Right Data Empty (trde)—bit 15203................................................................................................................................................................
Programming Considerations204................................................................................................................................................................
Sai State Machine205................................................................................................................................................................
Section 7 General Purpose Input/output207................................................................................................................................................................
Gpior Data Bits (gd[3:0])—bits 3–0210................................................................................................................................................................
Figure 7-2 Gpio Circuit Diagram211................................................................................................................................................................
A.1 Introduction215................................................................................................................................................................
A.3 Bootstrap Program Listing216................................................................................................................................................................
A.4 Bootstrap Flow Chart219................................................................................................................................................................
Appendix B Programming Reference221................................................................................................................................................................
B.1 Introduction223................................................................................................................................................................
Appendix C Application Examples251................................................................................................................................................................
C.1 Introduction253................................................................................................................................................................
C.3 Typical Audio Application254................................................................................................................................................................
C.4 Program Overlay255................................................................................................................................................................
C.6 Early Reflection Filter256................................................................................................................................................................
C.7 Two Channel Comb Filter257................................................................................................................................................................
C.8 3-tap Fir Filter260................................................................................................................................................................

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