Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled - Motorola DSP56305 User Manual

Program
$FFFFFF
$FF2000
Internal Program
$FF0800
$FF00C0
Bootstrap ROM
$FF0000
$001E00
$001A00
Internal Program
$000000
Program
RAM: 6.5 K
$000000–$0019FF
ROM: 6 K
$FF0800–$FF1FFF
Note: This column gives the maximum memory addressable in the memory space.

Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled

MOTOROLA
SC = 0, MS = 1, CE = 1
Internal $FFFFFF
Reserved
$FFFF80
ROM
6 K $FFF000
Internal
Reserved
192 words
$FF0000
External
$000B00
Instruction
Cache
1 K
RAM
6.5 K $000000
Memory Configuration
X Data
RAM: 2.75 K
$000000–$000AFF
N/A
ROM
DSP56305 User's Manual
Memory Configuration
X Data
Internal I/O $FFFFFF
128 words $FFFFC0
$FFFF80
External
$FFF000
Internal
Reserved $FF0C00
$FF0000
External
$000800
Internal
X data RAM
2.75 K
$000000
Y Data
RAM: 2 K
$000000–$0007FF
ROM: 3 K
$FF0000–$FF0BFF
Memory Maps
Y Data
External I/O
64 words
Internal I/O
64 words
External
Internal
Reserved
Internal
Y data ROM
3 K
External
Internal
Y data RAM
2 K
Max.
Cache
*
Mem.
1 K 16 M
$001A00–
$001DFF
3-15