Motorola DSP56305 User Manual page 248

Table 6-18 Host Port Signals - Detailed Description (Sheet 8 of 13)
HI32
Port
PCI
a
Pin
HSERR
System Error
Active low, open drain output
b
signal .
Used for reporting address parity
errors and other errors where the
result will be catastrophic. Asserted
for a single PCI clock by the HI32.
HI32 Mode
Enhanced Universal
HIRQ
Host Interrupt Request
b
Active low, output signal .
Used by the HI32 to request service from the host
processor. HIRQ may be connected to an interrupt request
signal of a host processor, a transfer request of a DMA
controller or a control input of external circuitry.
HIRQ is initially asserted by the HI32 when an interrupt
request is enabled (TREQ = 1 or RREQ = 1) and the
corresponding data path is ready for a data transfer.
If the HIRH bit in the DCTR is cleared: HIRQ assertion is a
pulse who's width is controlled by the CLAT register.
If HIRH is set: HIRQ is deasserted at the beginning of a
corresponding host data access (read or write), or masked
(by TREQ = 0 or RREQ = 0) or disabled (DMAE = 1).
HIRQ will be asserted again, after the host access
(regardless of the HIRH value), if enabled and the
corresponding data path is ready for a data transfer.
The HIRQ drive (driven or open drain) is controlled by the
HIRD bit in the DCTR.
b
Universal
GPIO
Disconnected