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In personal software reset APER does not reflect new address parity errors.
Hardware and software resets clear APER.
6.5.6.6
Data Parity Error (DPER) Bit 6
The DPER bit indicates that a data parity error has been detected (by the HI32 hardware,
or reported by the external host (HPERR asserted)), when in the PCI mode (HM = $1)
and the HI32 is a PCI master or selected target. At the end of a transaction, if a data
parity error has been detected, DPER is set and, if PEIE is set, a parity error interrupt
request is generated. DPER is cleared when it is written one by the DSP56300 core.
In personal software reset DPER does not reflect new data parity errors.
Hardware and software resets clear DPER.
6.5.6.7
Master Abort (MAB) Bit 7
The MAB bit indicates that a PCI transaction, initiated by the HI32, was terminated with
master abort. When a PCI transaction initiated by the HI32 is terminated with master
abort, MAB is set and, if TAIE is set, a transaction abort interrupt request is generated.
MAB is cleared when written one by the DSP56300 core.
If a PCI transaction, initiated by the HI32, was terminated with master abort, the
received master abort bit (RMA) in the CSTR is also set.
Hardware and software resets clear MAB.
6.5.6.8
Target Abort (TAB) Bit 8
The TAB bit indicates that a PCI transaction, initiated by the HI32, was terminated with
target abort. When a PCI transaction initiated by the HI32 is terminated with target
abort, TAB is set and, if TAIE is set, a transaction abort interrupt request is generated.
TAB is cleared when written one by the DSP56300 core.
If a PCI transaction, initiated by the HI32, was terminated with target abort, the received
target abort bit (RTA) in the CSTR is also set.
Hardware and software resets clear TAB.
6.5.6.9
Target Disconnect (TDIS) Bit 9
The TDIS bit indicates that a PCI transaction, initiated by the HI32, was terminated with
a target initiated disconnect. When a PCI transaction initiated by the HI32 is terminated
with disconnect, TDIS is set and, if TTIE is set, a transaction termination interrupt
request is generated. TDIS is cleared when written one by the DSP56300 core.
Hardware and software resets clear TDIS.
MOTOROLA
DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
6-41
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