Motorola DSP56305 User Manual

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DSP56305
24-Bit Digital Signal Processor
User's Manual
Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598

   Related Manuals for Motorola DSP56305

   Summary of Contents for Motorola DSP56305

  • Page 1

    DSP56305 24-Bit Digital Signal Processor User’s Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598...

  • Page 2

    Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended.

  • Page 3: Table Of Contents

    MANUAL CONVENTIONS ......1-5 DSP56305 FEATURES ....... 1-6 DSP56305 CORE DESCRIPTION .

  • Page 4: Table Of Contents

    3.2.1.1 Sample Code for DSP56305 Patch Mechanism..3-8 MEMORY CONFIGURATIONS ......3-10 3.3.1...

  • Page 5: Table Of Contents

    PreDivider Factor Bits (PD3:0)—PCTL Bits 20–23 ..4-24 DEVICE IDENTIFICATION REGISTER ....4-24 MOTOROLA DSP56305 User’s Manual...

  • Page 6: Table Of Contents

    Host Interrupt Request Drive Control (HIRD) Bit 19 ..6-16 6.5.1.13 HI32 Mode (HM2-HM0) Bits 22-20 ....6-17 DSP56305 User’s Manual MOTOROLA...

  • Page 7: Table Of Contents

    In a PCI Host-to-DSP Transaction: ....6-31 6.5.3.5.1 If FC = $0 (32-bit data mode): ....6-31 MOTOROLA DSP56305 User’s Manual...

  • Page 8: Table Of Contents

    HOST SIDE PROGRAMMING MODEL....6-48 6.6.1 HI32 Control Register (HCTR) ..... . 6-54 DSP56305 User’s Manual MOTOROLA...

  • Page 9: Table Of Contents

    Wait Cycle Control (WCC) Bit 7 ....6-80 6.6.8.5 System Error Enable (SERE) Bit 8 ....6-81 MOTOROLA DSP56305 User’s Manual...

  • Page 10: Table Of Contents

    INTERRUPT VECTORS ......6-107 6.10 VIA PROGRAMMING ......6-107 viii DSP56305 User’s Manual MOTOROLA...

  • Page 11: Table Of Contents

    Serial Control Direction 2 (SCD2) CRB Bit 4 ..7-22 7.4.2.5 Clock Source Direction (SCKD) CRB Bit 5 ... 7-22 MOTOROLA DSP56305 User’s Manual...

  • Page 12: Table Of Contents

    ESSI Transmit Shift Registers..... . . 7-40 7.4.7 ESSI Transmit Data Registers ..... . 7-41 DSP56305 User’s Manual MOTOROLA...

  • Page 13: Table Of Contents

    SCI Shift Direction (SSFTD) SCR Bit 3 ....8-10 8.3.1.3 Send Break (SBK) SCR Bit 4 ..... 8-10 MOTOROLA DSP56305 User’s Manual...

  • Page 14: Table Of Contents

    SCI Initialization Example ......8-27 8.4.4 Preamble, Break, and Data Transmission Priority ..8-28 DSP56305 User’s Manual MOTOROLA...

  • Page 15: Table Of Contents

    Prescaler Clock Enable (PCE) — TCSR Bit 15 ..9-16 9.3.3.11 Timer Overflow Flag (TOF) — TCSR Bit 20 ..9-16 MOTOROLA DSP56305 User’s Manual xiii...

  • Page 16: Table Of Contents

    GO Command (GO) Bit 6 ......10-6 10.4.1.4 Read/Write Command (R/W) Bit 7 ....10-6 DSP56305 User’s Manual MOTOROLA...

  • Page 17: Table Of Contents

    External Debug Request During RESET Assertion ..10-16 10.7.2 External Debug Request During Normal Activity ..10-16 10.7.3 Executing the JTAG DEBUG_REQUEST Instruction ..10-17 MOTOROLA DSP56305 User’s Manual...

  • Page 18: Table Of Contents

    11.3 TAP CONTROLLER ....... . 11-6 DSP56305 User’s Manual MOTOROLA...

  • Page 19: Table Of Contents

    DSP56300 RESTRICTIONS ......11-12 11.5 DSP56305 BOUNDARY SCAN REGISTER ... . . 11-13 SECTION 12 FILTER CO-PROCESSOR .

  • Page 20: Table Of Contents

    INTRODUCTION ........13-3 xviii DSP56305 User’s Manual MOTOROLA...

  • Page 21: Table Of Contents

    Decoding Enable (DECEN)—VCRA Bit 2 ... 13-19 13.5.3.4 Encoding Enable (ENCEN)—VCRA Bit 3 ... 13-19 13.5.3.5 Equalization Enable (EQEN)—VCRA Bit 4 ..13-19 MOTOROLA DSP56305 User’s Manual...

  • Page 22: Table Of Contents

    Reserved Bit—VTPA Bit 15 ..... 13-25 13.5.8 Viterbi Tap Register B (VTPB) ..... 13-26 DSP56305 User’s Manual MOTOROLA...

  • Page 23: Table Of Contents

    Parity Coding Modes Register Configuration... . 14-5 14.4 CCOP PROGRAMMING MODEL ..... . 14-6 MOTOROLA DSP56305 User’s Manual...

  • Page 24: Table Of Contents

    Input FIFO Empty bit (INFE)—CCSR Bit 20..14-18 14.4.4.13 Output FIFO Not Empty bit (OFNE)—CCSR Bit 21 . . . 14-18 14.4.4.14 Cipher Done bit (CIDN)—CCSR Bit 22 ... . 14-18 xxii DSP56305 User’s Manual MOTOROLA...

  • Page 25: Table Of Contents

    BOOTSTRAP CODE ......A-1 BOOTSTRAP CODE FOR THE DSP56305....A-2 MOTOROLA DSP56305 User’s Manual...

  • Page 26: Table Of Contents

    PROGRAMMING REFERENCE SHEETS ....D-16 QUICK REFERENCE TABLES ......D-43 xxiv DSP56305 User’s Manual MOTOROLA...

  • Page 27: Table Of Contents

    Identification Register Configuration (DSP56305 Revision 0) ....... . . 4-24 Figure 4-6 JTAG Identification Register Configuration (Revision 0) .

  • Page 28

    Figure 7-11 ESSI Receive Slot Mask Register A (RSMA) (ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2) ..... 7-14 xxvi DSP56305 User’s Manual MOTOROLA...

  • Page 29: Table Of Contents

    SCI Baud Rate Generator ....... . 8-19 MOTOROLA DSP56305 User’s Manual xxvii...

  • Page 30: Table Of Contents

    Figure 11-2 TAP Controller State Machine ......11-6 xxviii DSP56305 User’s Manual MOTOROLA...

  • Page 31: Table Of Contents

    Block Diagram of a Typical Data Communication System ..13-3 Figure 13-2 Ungerboeck Form of MLSE Channel Equalizer....13-4 MOTOROLA DSP56305 User’s Manual xxix...

  • Page 32: Table Of Contents

    Step Function Table B Register (CSFTB) ....14-13 Figure 14-8 CCOP Control Status Register (CCSR) ..... 14-15 DSP56305 User’s Manual MOTOROLA...

  • Page 33

    GSM Fire Decode ........14-31 MOTOROLA DSP56305 User’s Manual xxxi...

  • Page 34

    DSP56305 User’s Manual MOTOROLA...

  • Page 35

    On Chip Memory ........1-12 Table 2-1 DSP56305 Functional Signal Groupings ..... 2-3 Table 2-2 Power Inputs .

  • Page 36

    Memory Locations for Data RAM ......3-11 Table 4-1 DSP56305 Operating Modes .......4-4 Table 4-2 Interrupt Sources .

  • Page 37

    R/W Bit Definition ........10-6 MOTOROLA DSP56305 User’s Manual xxxiii...

  • Page 38

    JTAG Instructions ........11-8 Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions ..11-13 Table 12-1 FCOP Programming Model .

  • Page 39

    Operations During Cipher Mode Processing ....14-25 Table 14-8 Operations During Parity Coding Processing ....14-26 MOTOROLA DSP56305 User’s Manual xxxv...

  • Page 40

    DSP56305 User’s Manual MOTOROLA...

  • Page 41: Section 1 Dsp56305 Overview

    SECTION 1 DSP56305 OVERVIEW MOTOROLA DSP56305 User’s Manual...

  • Page 42: Table Of Contents

    Manual Conventions ....... . . 1-5 DSP56305 Features ....... . . 1-6 DSP56305 Core Description .

  • Page 43: Introduction, Manual Organization

    These documents, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the back cover of this document.

  • Page 44

    – Describes the On-Chip Emulation (OnCE™) module, accessed through the JTAG port SECTION 11—JTAG PORT – Describes the specifics of the JTAG port on the DSP56305 APPENDIX A—BOOTSTRAP PROGRAM – Lists the bootstrap code used for the DSP56305 APPENDIX B—EQUATES –...

  • Page 45: Manual Conventions

    – In code examples, have a tilde in front of their names. In the example on the following page, line 3 refers to the SS0 pin (shown as ~SS0). • Sets of pins or signals are indicated by the first and last pins or signals in the set, for instance HA1–HA8. MOTOROLA DSP56305 User’s Manual...

  • Page 46: Dsp56305 Features

    – the reset function, written as reset. DSP56305 FEATURES The DSP56305 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56305 uses the DSP56300 core, a high performance, single clock cycle per instruction engine. It provides up to twice the performance of Motorola's popular DSP56000 core family, while retaining code compatibility with that family.

  • Page 47: Dsp56305 Core Description, General Features, Hardware Debugging Support, Reduced Power Dissipation

    DSP56305 Overview DSP56305 Core Description DSP56305 CORE DESCRIPTION Core features are described fully in the . Pinout, memory, and DSP56300 Family Manual peripheral features are described in this manual. 1.5.1 General Features • 80 Million Instructions Per Second (MIPS) with an 80 MHz clock at 3.3 V •...

  • Page 48: Dsp56300 Core Functional Blocks, Data Alu, Data Alu Registers

    • Program Control Unit (PCU) • PLL and Clock Oscillator • JTAG Test Access Port (TAP) and On-Chip Emulation (OnCE) module • Memory In addition, the DSP56305 provides a set of on-chip peripherals, described in Section 1.8 1.6.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.

  • Page 49: Multiplier-accumulator (mac), Address Generation Unit (agu)

    The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output. MOTOROLA DSP56305 User’s Manual...

  • Page 50: Program Control Unit (pcu)

    • On-chip memory-expandable hardware stack • Nested hardware DO loops • Fast auto-return interrupts The PCU implements its functions using the following registers: • PC—Program Counter register • SR—Status Register • LA—Loop Address register • LC—Loop Counter register 1-10 DSP56305 User’s Manual MOTOROLA...

  • Page 51: Pll And Clock Oscillator

    Architecture. Problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation supports circuit-board test strategies based on this standard. MOTOROLA DSP56305 User’s Manual 1-11...

  • Page 52: On-chip Memory

    2.75 K × 24-bit 2 K × 24-bit enabled enabled There are on-chip ROMs for program memory (6 K x 24-bit), bootstrap memory (192 words x 24-bit), and Y data memory (3 K x 24-bit). 1-12 DSP56305 User’s Manual MOTOROLA...

  • Page 53: Off-chip Memory Expansion, Internal Buses

    • Program Address Bus (PAB) for carrying program memory addresses throughout the core • X Memory Address Bus (XAB) for carrying X memory addresses throughout the core • Y Memory Address Bus (YAB) for carrying Y memory addresses throughout the core MOTOROLA DSP56305 User’s Manual 1-13...

  • Page 54: Dsp56305 Block Diagram, Figure 1-1 Dsp56305 Block Diagram

    MODC/IRQB RESET MODB/IRQC PINIT/NMI MODA/IRQD AA1366 Figure 1-1 DSP56305 Block Diagram Note: Memory sizes in the block diagram are default sizes, except for the I-Cache, which is disabled by default. See (On-Chip Memories) for more Section 1.6.6 details about memory size.

  • Page 55: Direct Memory Access (dma), Dsp56305 Architecture Overview, General Purpose I/o (gpio) Functionality

    • Triggering from interrupt lines and all peripherals 1.10 DSP56305 ARCHITECTURE OVERVIEW The DSP56305 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56305 provides the following peripherals: •...

  • Page 56: Host Interface (hi32), Enhanced Synchronous Serial Interface (essi)

    1.10.3 Enhanced Synchronous Serial Interface (ESSI) The DSP56305 provides two independent and identical Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1). Each ESSI provides a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI.

  • Page 57: Serial Communications Interface (sci), Timer/event Counter (tec)

    MHz clock). The asynchronous protocols supported by the SCI include a Multidrop mode for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. This mode allows the DSP56305 to share a single serial line efficiently with other peripherals.

  • Page 58

    DSP56305 Overview DSP56305 Architecture Overview 1-18 DSP56305 User’s Manual MOTOROLA...

  • Page 59: Section 2 Signal/connection Descriptions

    SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS MOTOROLA DSP56305 User’s Manual...

  • Page 60

    Timers ......... . . 2-36 2.13 JTAG/OnCE Interface ....... 2-38 DSP56305 User’s Manual MOTOROLA...

  • Page 61: Signal Groupings

    Table 2-1 and as illustrated in Figure 2-1. The DSP56305 is operated from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.

  • Page 62: Figure 2-1 Signals Identified By Functional Group

    The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0–PC5), Port D GPIO signals (PD0–PD5), and Port E GPIO signals (PE0–PE2), respectively. TIO0–TIO2 can be configured as GPIO signals. AA0355 Figure 2-1 Signals Identified by Functional Group DSP56305 User’s Manual MOTOROLA...

  • Page 63: Figure 2-2 Host Interface/port B Detail Signal Diagram

    Leave unconnected PVCL Note: HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Motorola DSPs. AA1407 Figure 2-2 Host Interface/Port B Detail Signal Diagram MOTOROLA...

  • Page 64: Power

    V to each other internally. On those packages, all power input, except V , are labeled V . The number of connections indicated in this table are minimum values; the total V connections are package-dependent. DSP56305 User’s Manual MOTOROLA...

  • Page 65: Ground

    These designations are package-dependent. Some packages connect all GND inputs except GND to each other internally. On those packages, all power input, except GND and GND , are labeled GND. The number of connections indicated in this table are minimum values; the total GND connections are package-dependent. MOTOROLA DSP56305 User’s Manual...

  • Page 66: Clock, Phase Lock Loop (pll)

    If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. DSP56305 User’s Manual MOTOROLA...

  • Page 67: External Memory Expansion Port (port A)

    Table 2-8, External Bus Control Signals on the following pages detail the signals relevant to Port A, the external memory expansion port. When the DSP56305 enters a low-power standby mode (Stop or Wait), it releases bus mastership and tri-states the relevant Port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BS, CAS, BCLK, and BCLK.

  • Page 68: External Address Bus, External Data Bus

    Signal Description Name Reset, Wait, or Stop D0–D23 Input/ Tri-stated Data Bus—When the DSP is the bus master, Output D0–D23 provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0–D23 are tri-stated. 2-10 DSP56305 User’s Manual MOTOROLA...

  • Page 69: External Bus Control

    “early bus start” signal for a bus controller. If the external bus is not used during an instruction cycle, BS remains deasserted until the next external bus cycle. MOTOROLA DSP56305 User’s Manual 2-11...

  • Page 70

    Transfer Acknowledge—If the DSP56305 is the bus Input master and there is no external bus activity, or if the DSP56305 is not the bus master, TA is ignored. TA is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,..., infinity) may be added to...

  • Page 71

    DSP or the DMA no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56305 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56305 is the bus master (see the description of bus “parking”...

  • Page 72

    Column Address Strobe—When the DSP is the bus master, CAS is used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated. 2-14 DSP56305 User’s Manual MOTOROLA...

  • Page 73: Interrupt And Mode Control

    INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. MOTOROLA DSP56305 User’s Manual 2-15...

  • Page 74

    WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop standby state and IRQA is asserted, the processor will exit the Stop state. These inputs are 5 V tolerant. 2-16 DSP56305 User’s Manual MOTOROLA...

  • Page 75

    WAIT instruction and asserting IRQC to exit the Wait state. If the processor is in the Stop standby state and IRQC is asserted, the processor will exit the Stop state. These inputs are 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-17...

  • Page 76: Host Port Configuration, Host Interface (hi32)

    The functions of the signals associated with the HI32 vary according to the programmed configuration of the interface as determined by the 24-bit DSP Control Register (DCTR). Refer to the DSP56305 User’s Manual for detailed descriptions of this and the other configuration registers used with the HI32.

  • Page 77

    PB8–PB15 Input or Port B 8–15—When the HI32 is configured as Output GPIO through the DCTR, these signals are individually programmed as inputs or outputs through the HI32 DIRH. These inputs are 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-19...

  • Page 78

    Input or Port B 20—When the HI32 is configured as GPIO Output through the DCTR, this signal is individually programmed as an input or output through the HI32 DIRH. This input is 5 V tolerant. 2-20 DSP56305 User’s Manual MOTOROLA...

  • Page 79

    Input or Port B 22—When the HI32 is configured as GPIO Output through the DCTR, this signal is individually programmed as an input or output through the HI32 DIRH. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-21...

  • Page 80

    HI function is selected, this signal is Host DMA Acknowledge Schmitt-trigger input. Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 2-22 DSP56305 User’s Manual MOTOROLA...

  • Page 81

    HI function is selected, this signal is Host Address Enable input. Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-23...

  • Page 82

    HI function is selected, this signal is Host Interrupt Request output. Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 2-24 DSP56305 User’s Manual MOTOROLA...

  • Page 83

    HI function is selected, this signal is Host Data Read/Host Data Strobe Schmitt-trigger input. Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-25...

  • Page 84

    V Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 2-26 DSP56305 User’s Manual MOTOROLA...

  • Page 85

    Host Interrupt A—When the HI function is open selected, this signal is the Interrupt A open-drain drain output. Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-27...

  • Page 86

    There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola Serial Peripheral Interface (SPI). 2-28 DSP56305 User’s Manual...

  • Page 87

    Port C 1—The default configuration following Output reset is GPIO input PC1. When configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-29...

  • Page 88

    Port C 2—The default configuration following Output reset is GPIO input PC2. When configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input is 5 V tolerant. 2-30 DSP56305 User’s Manual MOTOROLA...

  • Page 89

    Port C 4—The default configuration following Output reset is GPIO input PC4. When configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-31...

  • Page 90

    GPIO input PD0. When configured as PD0, signal direction is controlled through the Port Directions Register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port Control Register (PCR1). This input is 5 V tolerant. 2-32 DSP56305 User’s Manual MOTOROLA...

  • Page 91

    Port D 2—The default configuration following reset is GPIO input PD2. When configured as Output PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-33...

  • Page 92

    Port D 4—The default configuration following reset is GPIO input PD4. When configured as Output PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. This input is 5 V tolerant. 2-34 DSP56305 User’s Manual MOTOROLA...

  • Page 93: Serial Communication Interface (sci)

    PE0, signal direction is controlled through the SCI Port Directions Register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port Control Register (PCR). This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-35...

  • Page 94: Timers

    Three identical and independent timers are implemented in the DSP56305. Each timer can use internal or external clocking, and can interrupt the DSP56305 after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events.

  • Page 95

    The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 2 Control/Status Register (TCSR2). This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-37...

  • Page 96: Jtag/once Interface

    Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. Always assert TRST immediately after power-up. This input is 5 V tolerant. 2-38 DSP56305 User’s Manual MOTOROLA...

  • Page 97

    Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input is 5 V tolerant. MOTOROLA DSP56305 User’s Manual 2-39...

  • Page 98

    Signal/Connection Descriptions JTAG/OnCE Interface 2-40 DSP56305 User’s Manual MOTOROLA...

  • Page 99: Section 3 Memory Configuration

    SECTION 3 MEMORY CONFIGURATION MOTOROLA DSP56305 User’s Manual...

  • Page 100

    Memory Maps ........3-11 Internal and External I/O Memory Map ....3-20 DSP56305 User’s Manual MOTOROLA...

  • Page 101: Memory Spaces, Program Memory Space

    0s in the most significant byte of the usual (24-bit) program and data word, and ignores the zeroed byte, thus effectively using 16-bit program and data words. The Sixteen-bit Compatibility mode allows the DSP56305 to use 56000 object code without change (thus minimizing system cost for applications that use the smaller address space).

  • Page 102: Program Ram, Bootstrap Rom

    The Program ROM usually contains the Real Time Operating System (RTOS), but may contain customer-supplied code. For further information on supplying code for a customized DSP56305 Program ROM, please contact your Motorola regional sales office. Program memory space at locations $FF00C0–$FF07FF and $FF2000–$FFFFFF is reserved and should not be accessed.

  • Page 103: Data Memory Spaces, X Data Memory Space

    Data memory space is divided into X data memory and Y data memory to match the natural partitioning of DSP algorithms. The data memory partitioning allows the DSP56305 to feed two operands to the Data ALU simultaneously, enabling it to perform a multiply-accumulate operation in one clock cycle.

  • Page 104: Y Data Memory Space, Memory Space Configuration

    3.1.3 Memory Space Configuration Memory space addressing is for 24-bit words by default. The DSP56305 switches to Sixteen-bit Address Compatibility mode by setting the Sixteen-bit Compatibility (SC) bit in the Status Register (SR). Table 3-1 Memory Space Configuration Bit Settings for the DSP56305...

  • Page 105: Ram Configuration

    Memory Configuration RAM Configuration RAM CONFIGURATION The DSP56305 contains 12.25 K of RAM, divided by default into: • Program RAM (6.5 K) • X data RAM (3.75 K) • Y data RAM (2.0 K) RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the Memory Select (MS) of the OMR.

  • Page 106: Dsp56300 Ram Patch Mechanism, Sample Code For Dsp56305 Patch Mechanism

    5. write the desired replacement data to the (virtual) patch locations 6. reading (or fetching) the location to be replaced will then return the replacement data instead of the ROM data 3.2.1.1 Sample Code for DSP56305 Patch Mechanism M_PROMS $ff0800 ; ROM area Start...

  • Page 107: Memory Configuration

    ; 5 - read with hit #(M_PROME-M_PROMS+1) move p:(r0)+,x0 ; 2 - fetch ; 6 - fetch with hit move #M_PROMS,r0 ; ROM: rts (to the ENDTEST) ENDTEST jmp ENDTEST ; patch data PATCH_DATA_START move #5,m0 move #6,m1 move #7,m2 PATCH_DATA_END MOTOROLA DSP56305 User’s Manual...

  • Page 108: Memory Configurations, Memory Space Configurations, Ram Configurations

    16 M words $000000–$FFFFFF 64 K words $0000–$FFFF 3.3.2 RAM Configurations The RAM configurations for the DSP56305 are listed in Table 3-4. Table 3-4 RAM Configurations for the DSP56305 Bit Settings Memory Sizes (in K) Program X data Y data Cache 3.75...

  • Page 109: Memory Maps

    The following figures describe each of the memory space and RAM configurations defined by the settings of the SC, MS, and CE bits. The figures show the configuration and the table describes the bit settings, memory sizes, and memory locations. MOTOROLA DSP56305 User’s Manual 3-11...

  • Page 110: Figure 3-1 Default Memory Configuration

    RAM: 3.75 K RAM: 2 K None 16 M $000000–$0019FF $000000–$000EFF $000000–$0007FF ROM: 6 K ROM: 3 K $FF0800–$FF1FFF $FF0000–$FF0BFF Note: This column gives the maximum memory addressable in the memory space. Figure 3-1 Default Memory Configuration 3-12 DSP56305 User’s Manual MOTOROLA...

  • Page 111: Figure 3-2 Instruction Cache Enabled

    RAM: 2 K 16 M $000000–$0015FF $000000–$000EFF $000000–$0007FF $001600– $0019FF ROM: 6 K ROM: 3 K $FF0800–$FF1FFF $FF0000–$FF0BFF Note: This column gives the maximum memory addressable in the memory space. Figure 3-2 Instruction Cache Enabled MOTOROLA DSP56305 User’s Manual 3-13...

  • Page 112: Figure 3-3 Memory Switch Enabled

    RAM: 2.75 K RAM: 2 K None 16 M $000000–$001DFF $000000–$000AFF $000000–$0007FF ROM: 6 K ROM: 3 K $FF0800–$FF1FFF $FF0000–$FF0BFF Note: This column gives the maximum memory addressable in the memory space. Figure 3-3 Memory Switch Enabled 3-14 DSP56305 User’s Manual MOTOROLA...

  • Page 113: Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled

    16 M $000000–$0019FF $000000–$000AFF $000000–$0007FF $001A00– $001DFF ROM: 6 K ROM: 3 K $FF0800–$FF1FFF $FF0000–$FF0BFF Note: This column gives the maximum memory addressable in the memory space. Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled MOTOROLA DSP56305 User’s Manual 3-15...

  • Page 114: Figure 3-5 Sixteen-bit Compatibility Mode

    Y Data Cache Mem. RAM: 6.5 K RAM: 3.75 K RAM: 2 K None 64 K $0000–$19FF $0000–$0EFF $0000–$07FF Note: This column gives the maximum memory addressable in the memory space. Figure 3-5 Sixteen-Bit Compatibility Mode 3-16 DSP56305 User’s Manual MOTOROLA...

  • Page 115: Figure 3-6 Sixteen-bit Compatibility Mode, Instruction Cache Enabled

    RAM: 5.5 K RAM: 3.75 K RAM: 2 K 64 K $0000–$15FF $0000–$0EFF $0000–$07FF $1600–$19FF Note: This column gives the maximum memory addressable in the memory space. Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled MOTOROLA DSP56305 User’s Manual 3-17...

  • Page 116: Figure 3-7 Sixteen-bit Compatibility Mode, Memory Switch Enabled

    RAM: 7.5 K RAM: 2.75 K RAM: 2 K None 64 K $0000–$1DFF $0000–$0AFF $0000–$07FF Note: This column gives the maximum memory addressable in the memory space. Figure 3-7 Sixteen-Bit Compatibility Mode, Memory Switch Enabled 3-18 DSP56305 User’s Manual MOTOROLA...

  • Page 117: Instruction Cache Enabled

    RAM: 2.75 K RAM: 2 K 64 K $0000–$19FF $0000–$0AFF $0000–$07FF $1A00–$1DFF Note: This column gives the maximum memory addressable in the memory space. Figure 3-8 Sixteen-Bit Compatibility Mode, Memory Switch Enabled, Instruction Cache Enabled MOTOROLA DSP56305 User’s Manual 3-19...

  • Page 118: Internal And External I/o Memory Map

    Internal and External I/O Memory Map INTERNAL AND EXTERNAL I/O MEMORY MAP The DSP56305 internal I/O space (the top 128 locations of the X data memory space and 64 high Y data memory space locations) and external I/O space (the top 64 locations of Y data memory space) are listed in Appendix D, Table D-2.

  • Page 119: Section 4 Core Configuration, Core Configuration

    SECTION 4 CORE CONFIGURATION MOTOROLA DSP56305 User’s Manual...

  • Page 120: Table Of Contents

    JTAG Identification (ID) Register ..... . . 4-25 4.11 JTAG Boundary Scan Register (BSR)....4-25 DSP56305 User’s Manual MOTOROLA...

  • Page 121: Operating Modes, Introduction

    The DSP56305 begins operations by leaving Reset and going into one of eight operating modes. As the DSP56305 exits the Reset state it loads the values of MODA, MODB, MODC, and MODD into bits MA, MB, MC, and MD of the Operating Mode Register (OMR).

  • Page 122

    Core Configuration Operating Modes Table 4-1 DSP56305 Operating Modes Reset Mode MODD MODC MODB MODA Description Vector $C00000 Expanded mode $FF0000 RTOS Mode $FF0000 RTOS Mode $FF0000 RTOS Mode $FF0000 Reserved $FF0000 Reserved $FF0000 Reserved $FF0000 Reserved $008000 Expanded mode...

  • Page 123: Bootstrap Program

    3. Otherwise, the DSP56305 jumps to the bootstrap program entry point at $FF0000. If the bootstrap program is loading via the Host Interface (HI32), setting the HF0 bit in the HSR causes the DSP56305 to stop loading and begin execution of the loaded program at the specified start address.

  • Page 124: Mode 0: Expanded Mode

    Vector $C00000 Expanded mode The bootstrap ROM is bypassed and the DSP56305 starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. DSP56305 User’s Manual...

  • Page 125: Modes 1–3: Bootstrap According To Rtos Mode, Modes 4–7: Reserved

    MODA, MODB, and MODC. 4.3.3 Modes 4–7: Reserved Reset Mode MODD MODC MODB MODA Description Vector — Reserved — Reserved — Reserved — Reserved These modes are reserved for future use. MOTOROLA DSP56305 User’s Manual...

  • Page 126: Mode 8: Expanded Mode, Mode 9: Bootstrap From Byte-wide External Memory

    Description Vector $008000 Expanded mode The bootstrap ROM is bypassed and the DSP56305 starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. 4.3.5 Mode 9: Bootstrap From Byte-Wide External Memory...

  • Page 127: Mode C: Bootstrap Through Hi32 In Pci Mode

    MODD, bootstraps through HI32 in 24-bit wide UB slave mode, in a configuration that allows glueless connection to Port A of a DSP563xx device. The DSP56305 is written with 24-bit wide words reflecting the 24-bit wide host bus transfers. This mode may be used for booting a slave DSP56305 from Port A of a master DSP563xx device with glueless connection.

  • Page 128: Double-strobe Pin Configuration

    The DSP56305 is written with 24-bit wide words broken into 8-bit wide host bus transfers. This mode may be used for booting from various microprocessors or microcontrollers, as for booting a slave DSP56305 from Port A of a master DSP563xx device.

  • Page 129: Single-strobe Pin Configuration, Rtos Program, Interrupt Sources And Priorities

    OMR to determine the program flow. INTERRUPT SOURCES AND PRIORITIES Interrupt handling by the DSP56305, like that of all DSP56300 family members, has been optimized for DSP applications. Refer to Section 7 of the DSP56300 Family Manual. The interrupt table is located in the 256 locations of program memory pointed to by the Vector Base Address (VBA) register in the Program Control Unit.

  • Page 130: Interrupt Sources

    The DSP56305 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. In the DSP56305, not all of the 128 vector addresses are used for specific interrupt sources. The remaining addresses are reserved. If it is known that certain interrupts will not be used, those interrupt vector locations may be used for program or data storage.

  • Page 131

    ESSI0 Receive Data VBA:$32 0–2 ESSI0 Receive Data With Exception Status VBA:$34 0–2 ESSI0 Receive last slot VBA:$36 0–2 ESSI0 Transmit Data VBA:$38 0–2 ESSI0 Transmit Data with Exception Status VBA:$3A 0–2 ESSI0 Transmit last slot MOTOROLA DSP56305 User’s Manual 4-13...

  • Page 132

    0–2 Host Slave Transmit Request VBA:$70 0–2 Host PCI Master Address Request VBA:$72 0–2 / 3 Host Command / Host NMI (Default) VBA:$74 0–2 Reserved VBA:$76 0–2 Reserved VBA:$78 0–2 FCOP Data Input Buffer Empty 4-14 DSP56305 User’s Manual MOTOROLA...

  • Page 133: Interrupt Priority Levels

    4.5.2 Interrupt Priority Levels The DSP56305 has a four level interrupt priority structure. Each interrupt has two Interrupt Priority Level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is the lowest priority level. Level 3 is the highest level priority and is non-maskable.

  • Page 134: Figure 4-1 Interrupt Priority Register C (ipr-c) (x:$ffffff)

    0, 1 0, 1, 2 There are two interrupt priority registers in the DSP56305. The IPR-C is dedicated to DSP56300 core interrupt sources and IPR-P is dedicated to DSP56305 peripheral interrupt sources. IPR-C is shown on Figure 4-1 on page 4-16 and IPR-P is shown in Figure 4-2 on page 4-17.

  • Page 135: Interrupt Source Priorities Within An Ipl, Figure 4-2 Interrupt Priority Register P (ipr-p) (x:$fffffe)

    IPL is serviced first. When several interrupt requests having the same IPL are pending, another fixed-priority structure within that IPL determines which interrupt source is serviced first. The fixed priority of interrupt sources within an IPL is listed in Table 4-4. MOTOROLA DSP56305 User’s Manual 4-17...

  • Page 136

    DMA Channel 4 Interrupt DMA Channel 5 Interrupt Host Command Interrupt Host PCI Transaction Termination Host PCI Transaction Abort Host PCI Parity Error Host PCI Transfer Complete Host PCI Master Receive Request Host Slave Receive Request 4-18 DSP56305 User’s Manual MOTOROLA...

  • Page 137

    SCI Receive Data with Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line SCI Timer TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt FCOP Data Input Buffer Empty MOTOROLA DSP56305 User’s Manual 4-19...

  • Page 138: Dma Request Sources

    DMA requests used to trigger DMA transfers. DMA request sources may be internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC, or IRQD signals. Table 4-5 describes the meanings of the DRS bits. 4-20 DSP56305 User’s Manual MOTOROLA...

  • Page 139

    FCOP Data Input Buffer Empty (FDIBE=1) 10100 FCOP Data Output Buffer Full (FDOBF=1) 10101 VCOP Input Data (DREQ=1) 10110 VCOP Output Buffer Full (DOBF=1) 10111 VCOP Output Data (DRDY=1) 11000 VCOP Processing Done (DONE=1) 11001 CCOP Input FIFO Empty (INFE=1) MOTOROLA DSP56305 User’s Manual 4-21...

  • Page 140: Operating Mode Register (omr), Address Tracing Enable (ate)—omr Bit 15, Operating Mode Register (omr)

    The Address Tracing Enable bit (ATE) is used to enable the Address Tracing mode, which allows the core to reflect the addresses of internal fetches and program space moves to the Address bus, providing assistance in software development. 4-22 DSP56305 User’s Manual MOTOROLA...

  • Page 141: Pll Control Register, Pll Multiplication Factor (mf11:0)—pctl Bits 0–11, Crystal Range (xtlr)—pctl Bit 15

    PLL Multiplication Factor (MF11:0)—PCTL Bits 0–11 The Multiplication Factor bits (MF[11:0]) define the Multiplication Factor (MF) that is applied to the PLL input frequency. The MF bits are cleared during DSP56305 hardware reset, which corresponds to an MF of one.

  • Page 142: Xtal Disable (xtld)—pctl Bit 16, Predivider Factor Bits (pd3:0)—pctl Bits 20–23, Device Identification Register

    Figure 4-5 gives the contents of the IDR for the DSP56305 Revision 0. The IDR for a specific mask can be found on the silicon errata sheet on the Motorola DSP Web page. Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, $2 is revision B, and so on.

  • Page 143: Jtag Identification (id) Register, Jtag Boundary Scan Register (bsr)

    (0000000101) b. The design center number, in bits 27–22, which for MSIL is $6 (000110) 4. The revision number, in bits 28–31, which for the DSP56305 Revision 0 is $0 (0000). The JTAG ID register value for the DSP56305 Revision 0 is $0180501D.

  • Page 144

    Core Configuration JTAG Boundary Scan Register (BSR) 4-26 DSP56305 User’s Manual MOTOROLA...

  • Page 145: Section 5 General Purpose I/o

    SECTION 5 GENERAL PURPOSE I/O MOTOROLA DSP56305 User’s Manual...

  • Page 146

    Programming Model ....... . . 5-3 DSP56305 User’s Manual MOTOROLA...

  • Page 147: Programming Model, Introduction, Port B Signals And Registers, Port C Signals And Registers

    Introduction INTRODUCTION The DSP56305 provides forty-two bidirectional signals that can be configured as General Purpose Input/Output (GPIO) signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The control register settings of the DSP56305’s peripherals determine whether these signals...

  • Page 148: Port D Signals And Registers, Port E Signals And Registers, Triple Timer Signals

    Each of the three Triple Timer Interface signals (TIO0–TIO2) not used as a timer signal can be configured individually as a GPIO signal. Each signal is controlled by the appropriate Timer Control Status register (TCSR0–TCSR2). These registers are described in Section 9 of this document. DSP56305 User’s Manual MOTOROLA...

  • Page 149: Section 6 Host Interface (hi32)

    HOST INTERFACE (HI32) SECTION 6 HOST INTERFACE (HI32) MOTOROLA DSP56305 User’s Manual...

  • Page 150

    HOST INTERFACE (HI32) DSP56305 User’s Manual MOTOROLA...

  • Page 151: Introduction To The Host Interface (hi32)

    In the General Purpose I/O (GPIO) mode, 24 of the HI32 signals may be programmed as GPIO signals. Host port signal functionality and polarity are controlled by the DSP56300 core programming the DSP Control Register (DCTR). MOTOROLA DSP56305 User’s Manual...

  • Page 152: Hi32 Features, Interface - Dsp56300 Core Side

    HOST INTERFACE (HI32) HI32 Features HI32 FEATURES The DSP56305 host interface features are discussed below as they apply to the Core Interface, the Host Interface, the PCI mode, and the UB mode. 6.2.1 Interface - DSP56300 Core Side • Mapping — 11 internal I/O data space memory locations •...

  • Page 153

    • Instructions – Memory mapped registers allow standard MOVE instruction for data transfer between DSP56305 and external hosts – Special MOVEP instruction provides for I/O service capability using fast interrupts, and provides faster execution with fewer instruction words –...

  • Page 154: Interface - Host Side

    • Semaphores: flags supplied for HI32 allocation in a multi-host system • Handshaking Protocols – PCI Mode Handshaking Protocols • Software Polled • PCI Interrupt (HINTA signal) • Data Acknowledge (HTRDY and HIRDY signals) • Bus Arbitration (HREQ and HGNT signals) DSP56305 User’s Manual MOTOROLA...

  • Page 155: Hi32 Features In Pci Mode

    • Supports high speed (fast peripheral) DSP56300 core DMA transfers (two core clock cycles per DMA transfer) • Supports memory-space and configuration transactions as a target • Supports memory-space, I/O-space and configuration transactions as an initiator • Supports exclusive (locked) accesses MOTOROLA DSP56305 User’s Manual...

  • Page 156: Hi32 Features In Universal Bus Modes

    • Supports an external data buffer for drive and voltage level compatibility with the external bus (e.g. ISA bus) • Generates interrupt requests: hardware driven (HIRQ) and software driven (HINTA) • Generates vectored DSP56300 core interrupts separately for receive and transmit events and host commands DSP56305 User’s Manual MOTOROLA...

  • Page 157: Hi32 Resets

    All host port signals, except HRST/HRST, are forced to the disconnected state: all outputs are high impedance, inputs are electrically disconnected. The DSP side state machines are not affected. The HRST/HRST signal is ignored in the self configuration mode. MOTOROLA DSP56305 User’s Manual...

  • Page 158: Hi32 Block Diagram, Figure 6-1 Hi32 Block Diagram

    PCI Configuration Space CDID CVID CSTR CCMR HCVR HSTR HCTR HTXR HRXM HRXS CCCR CRID CHTY CLAT CBMA CILP data transfer format converter HOST Bus Note: Five words in UBM Figure 6-1 HI32 Block Diagram 6-10 DSP56305 User’s Manual MOTOROLA...

  • Page 159: Dsp Side Programming Model

    The following paragraphs describe the purpose and operation of each bit in each register of the HI32 visible to the DSP56300 core. The effects of different reset types on these registers are shown. The HI32 host side programming model is described in Section 6.6. MOTOROLA DSP56305 User’s Manual 6-11...

  • Page 160: Dsp Control Register (dctr)

    All reserved bits are read as zeros and should be programmed as zeros for future compatibility. The bit manipulation instructions are useful for accessing individual bits in the DCTR. The DCTR bits are described in the following paragraphs. 6-12 DSP56305 User’s Manual MOTOROLA...

  • Page 161: Host Command Interrupt Enable (hcie) Bit 0, Slave Transmit Interrupt Enable (stie) Bit 1

    The HINT bit controls the HINTA signal. When HINT is set by the DSP56300 core, the HINTA signal is driven low. When HINT is cleared by the DSP56300 core, the HINTA signal is released. Hardware and software resets clear HINT. MOTOROLA DSP56305 User’s Manual 6-13...

  • Page 162: Host Data Strobe Mode (hdsm) Bit 13, Host Read/write Polarity (hrwp) Bit 14

    The value of HRWP may be changed only when HACT = 0. HRWP is ignored when not in a Universal Bus mode or double-strobe host port mode is ≠ selected (HM $2 or $3, or HDSM = 0). Hardware and software resets clear HRWP. 6-14 DSP56305 User’s Manual MOTOROLA...

  • Page 163: Host Transfer Acknowledge Polarity (htap) Bit 15, Host Dma Request Polarity (hdrp) Bit 16

    HRST signal is active low and the HI32 will be reset if HRST signal is low (i.e. asserted). The value of HRSP may be changed only when HACT = 0. HRSP is ignored in the PCI mode (HM = $1). Hardware and software resets clear HRSP. MOTOROLA DSP56305 User’s Manual 6-15...

  • Page 164: Host Interrupt Request Handshake Mode(hirh) Bit 18, Host Interrupt Request Drive Control (hird) Bit 19

    To assure proper operation, these signals may be changed only when HACT = 0. The HM2-HM0 bits must not be changed together with these bits (i.e. in the same core write). 6-16 DSP56305 User’s Manual MOTOROLA...

  • Page 165: Hi32 Mode (hm2-hm0) Bits 22-20, Terminate And Reset (hm[2:0] = 000)

    Configuration space transactions are affected by clearing the HM bits. CSID must be loaded, due to self configuration mode before the host can configure the DSP56305. In the personal software reset the HI32 consumes very little current. This is a low-power state.

  • Page 166: Pci Mode (hm = $1), Universal Bus Mode (hm = $2)

    Vcc or to GND respectively. For example: when operating with a 16-bit bus (e.g. ISA bus), HP48-HP41 must be forced or pulled up to Vcc or pulled down to GND. 6-18 DSP56305 User’s Manual MOTOROLA...

  • Page 167: Enhanced Universal Bus Mode (hm = $3):, Gpio Mode (hm = $4):

    (i.e. in the same core write) with any of the following bits: HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, or HIRD. The combinations HM = $6, HM = $7 are reserved for future expansion and should not be used. Hardware and software resets clear the HM bits. MOTOROLA DSP56305 User’s Manual 6-19...

  • Page 168: Dctr Reserved Control Bits 23, 12-7

    Vcc or to GND. b. Must be forced or pulled to Vcc or GND. HBS/HDAK should be forced or pulled up to Vcc if not used. d. Must be forced or pulled up to Vcc. 6-20 DSP56305 User’s Manual MOTOROLA...

  • Page 169: Dsp Pci Control Register (dpcr)

    All reserved bits are read as zeros and should be programmed as zeros for future compatibility. The bit manipulation instructions are useful for accessing individual bits in the DPCR. The DPCR bits are described in the following paragraphs. MOTOROLA DSP56305 User’s Manual 6-21...

  • Page 170: Master Transmit Interrupt Enable (mtie) Bit 1, Master Receive Interrupt Enable (mrie) Bit 2

    If TAIE is set, a transaction abort interrupt request will be generated if a transaction was terminated due to master-abort (MAB is set in the DPSR) or target-abort (TAB is set). Hardware and software resets clear TAIE. 6-22 DSP56305 User’s Manual MOTOROLA...

  • Page 171: Transaction Termination Interrupt Enable (ttie) Bit 9, Transfer Complete Interrupt Enable (tcie) Bit 12

    • No DSP56300 core DMA channel is enabled to service HI32 master transmit data DMA requests. CLRT is ignored when the HI32 is not in the PCI mode (HM≠$1). Hardware and software resets clear CLRT. MOTOROLA DSP56305 User’s Manual 6-23...

  • Page 172: Master Transaction Termination (mtt) Bit 15, System Error Force (serf) Bit 16

    SERF is ignored when the SERE bit is cleared or when the HI32 is not an active PCI agent (i.e. HM≠$1 or the HI32 is not the current PCI bus master or a selected target). Hardware and software resets clear SERF. 6-24 DSP56305 User’s Manual MOTOROLA...

  • Page 173: Master Access Counter Enable (mace) Bit 18, Master Wait State Disable (mwsd) Bit 19

    MWSD is ignored when the HI32 is not in the PCI mode (HM≠$1). The value of MWSD may be changed only when HACT = 0. Hardware and software resets clear MWSD. MOTOROLA DSP56305 User’s Manual 6-25...

  • Page 174: Receive Buffer Lock Enable (rble) Bit 20

    RBLE is ignored when the HI32 is not in the PCI mode (HM≠$1). The value of RBLE may be changed only when HACT = 0 or HDTC = 1. Hardware and software resets clear RBLE. 6-26 DSP56305 User’s Manual MOTOROLA...

  • Page 175: Insert Address Enable (iae) Bit 21

    Hardware and software resets clear IAE. 6.5.2.15 DPCR Reserved Control Bits 23, 22,17,13,11,10, 8, 6, 3, 0 These bits are reserved for future expansion, they are read as zeros and should be written with zeros for upward compatibility. MOTOROLA DSP56305 User’s Manual 6-27...

  • Page 176: Dsp Pci Master Control Register(dpmc), Dsp Pci Transaction Address (ar31-ar16) Bits 15-0

    HI32 will initiate a PCI transaction. The full 32-bit address (AR31-AR16 from the DPMC and AR15-AR0 from the DPAR) is driven to the HAD31-HAD0 signals during the PCI address phase. Hardware and software resets clear AR31-AR16. 6-28 DSP56305 User’s Manual MOTOROLA...

  • Page 177: Dsp Pci Data Burst Length (bl5-bl0) Bits 21-16

    The two least significant bytes of two HRXM locations All 32 PCI data bits are written to the HTXR as two are output. zero-extended 16-bit words. GDB/MDDB GDB/MDDB HI32 HI32 DTXM DRXR HRXM HTXR HDTFC HDTFC PCI bus PCI bus MOTOROLA DSP56305 User’s Manual 6-29...

  • Page 178

    The three least significant HRXM bytes are output left The three most significant PCI data bytes are written aligned and zero filled. to the HTXR. GDB/MDDB GDB/MDDB HI32 HI32 DTXM DRXR HRXM HTXR HDTFC HDTFC PCI bus PCI bus 6-30 DSP56305 User’s Manual MOTOROLA...

  • Page 179: In A Pci Dsp-to-host Transaction:, If Fc = $0 (32-bit Data Mode):

    32-bit word. 6.5.3.5.2 If FC = $1 or $2: The three least significant PCI data bytes from the HAD23-HAD0 signals are transferred to the DRXR to be read by the DSP56300 core. MOTOROLA DSP56305 User’s Manual 6-31...

  • Page 180: If Fc = $3:, Dsp Pci Address Register (dpar)

    PCI bus byte enables. The DPAR cannot be accessed by the host processor. The two most significant bytes of the PCI transaction address are located in the DSP PCI master control register (DPMC, see Section 6.5.3). 6-32 DSP56305 User’s Manual MOTOROLA...

  • Page 181: Pci Bus Command (c3-c0) Bits 11-8

    HI32 is in the PCI mode (HM=$1), ownership of the PCI bus is requested and, when granted, the address is driven to the HAD31-HAD0 signals and the bus command is driven to the HC3/HBE3-HC0/HBE0 signals during the PCI address phase. MOTOROLA DSP56305 User’s Manual 6-33...

  • Page 182: Pci Byte Enables (be3-be0) Bits 15-12

    The HI32, as master, drives all the HRXM data to the HAD31-HAD0 signals during write transactions, and writes the HAD31-HAD0 signals to the HTXR (in accordance with the FC1-FC0 bits) in read transactions, regardless of the BE3-BE0 value. Hardware and software resets clear BE3-BE0. 6-34 DSP56305 User’s Manual MOTOROLA...

  • Page 183: Dsp Status Register (dsr), Host Command Pending (hcp) Bit 0

    HI32. In the Pre-Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the STRQ status bit and generating core interrupt requests or DMA requests if enabled) whenever the DTXS is not full. MOTOROLA DSP56305 User’s Manual 6-35...

  • Page 184: Slave Receive Data Request (srrq) Bit 2

    • if SRIE is set, a slave receive data interrupt request is generated • if enabled by an DSP56300 core DMA channel, a slave receive data DMA request will be generated. Hardware, software and personal software resets clear SRRQ. 6-36 DSP56305 User’s Manual MOTOROLA...

  • Page 185: Host Flags (hf2-hf0) Bits 5-3, Hi32 Active (hact) Bit 23, Dsr Reserved Status Bits 22-6

    When HACT is set, the HI32 is active, and the DCTR mode and polarity bits must NOT be changed. Hardware and software resets clear HACT. 6.5.5.6 DSR Reserved Status Bits 22-6 These bits are reserved for future expansion and read as zeros. MOTOROLA DSP56305 User’s Manual 6-37...

  • Page 186: Dsp Pci Status Register (dpsr)

    The DPSR is a 24-bit read-only status register used by the DSP56300 core to examine the status and flags of the HI32, when in the PCI mode (HM=$1). The DPSR cannot be accessed by the host processor. The DPSR bits are described in the following paragraphs. 6-38 DSP56305 User’s Manual MOTOROLA...

  • Page 187: Pci Master Wait State (mws) Bit 0, Pci Master Transmit Data Request (mtrq) Bit 1

    • if enabled by an DSP56300 core DMA channel, a master transmit data DMA request will be generated. Hardware, software and personal software resets set MTRQ. In the personal software reset state MTRQ = 0. MOTOROLA DSP56305 User’s Manual 6-39...

  • Page 188: Pci Master Receive Data Request (mrrq) Bit 2, Master Address Request (marq) Bit 4

    (SSE) bit is set in the CSTR/CCMR. • the detected parity error bit (DPE) in the CSTR is set. APER is cleared when it is written one by the DSP56300 core. 6-40 DSP56305 User’s Manual MOTOROLA...

  • Page 189: Data Parity Error (dper) Bit 6, Master Abort (mab) Bit 7

    When a PCI transaction initiated by the HI32 is terminated with disconnect, TDIS is set and, if TTIE is set, a transaction termination interrupt request is generated. TDIS is cleared when written one by the DSP56300 core. Hardware and software resets clear TDIS. MOTOROLA DSP56305 User’s Manual 6-41...

  • Page 190: Target Retry (trty) Bit 10, Pci Time Out (to) Bit 11

    BSET command. The proper way to clear these bits is to write (MOVE(P) instruction) ones to the bits to be cleared and zeros to all the others. 6-42 DSP56305 User’s Manual MOTOROLA...

  • Page 191: Remaining Data Count (rdc5-rdc0) Bits 21-16, Dpsr Reserved Bits 23-22, 15-12 And 3

    24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR. The DSP side of the host-to-DSP data FIFO is described below. For a detailed description of the host side see Section 6.2.2. MOTOROLA DSP56305 User’s Manual 6-43...

  • Page 192: Dsp Receive Data Fifo (drxr), Dsp To Host Data Path

    HRXM, the 32-bits of significant data located in two words written to the DTXM are output. In PCI target data transfers (HM = $1) with HRF≠$0 and in Universal Bus mode data transfers, the slave DSP-to-host data path (DTXS-HRXS) is a six word deep FIFO. The 6-44 DSP56305 User’s Manual MOTOROLA...

  • Page 193: Dsp Master Transmit Data Register (dtxm)

    In the 32-bit mode (HM = $1 with FC = $0), only the two least significant bytes of the DTXM are transferred. (See Section 6.5.9, above, and Table 6-5). Hardware, software and personal software resets empty the DTXM. MOTOROLA DSP56305 User’s Manual 6-45...

  • Page 194: Dsp Slave Transmit Data Register (dtxs), Dsp Host Port Gpio Data Register (dath)

    DAT23-DAT0 are used to read or write data from/to the corresponding GPIO signal. The functionality of the DAT23-DAT0 bits is defined in Table 6-10. Hardware and software resets clear all DATH bits. 6-46 DSP56305 User’s Manual MOTOROLA...

  • Page 195: Dsp Host Port Gpio Direction Register (dirh)

    Read/write bit. The value written is the Read/write bit. The value written is the value read. The corresponding signal is value read. configured as an output, and is driven with the data written to DATx. defined by the selected mode MOTOROLA DSP56305 User’s Manual 6-47...

  • Page 196: Host Side Programming Model

    Vcc or to GND respectively. For example: when operating with a 16-bit bus (e.g. ISA bus), HP48-HP41 must be forced or pulled up to Vcc or pulled down to GND. 6-48 DSP56305 User’s Manual MOTOROLA...

  • Page 197

    • The HI32 will not reach dead-lock due to illegal PCI events. Illegal PCI events bring the HI32 Master and Target state machines to the IDLE state. • As a PCI target the HI32 executes the PCI bus command as described in Table 6-12: MOTOROLA DSP56305 User’s Manual 6-49...

  • Page 198

    CBMA HI32 configuration registers can also be accessed, indirectly, by the DSP56300 core in the Self Configuration mode (HM = $5 - see Section 6.5.1.13). Reserved addresses are read as zeros, and should be written with zeroes for future compatibility. 6-50 DSP56305 User’s Manual MOTOROLA...

  • Page 199

    IRQA, IRQB exception routines), and perform control and debugging operations if exception routines are implemented in the DSP to perform these tasks. The host processor can also generate non-maskable interrupt requests to the DSP56300 core using the host commands. MOTOROLA DSP56305 User’s Manual 6-51...

  • Page 200: Figure 6-2 Host Side Registers (pci Memory Address Space)

    Header Type (CHTY) Latency Timer (CLAT) $10(CBMA) Memory Space Base Address (CBMA) Reserved(58 Dwords) $FC(CILP) MAX_LAT MIN_GNT Interrupt Line Interrupt Signal Addresses shown are in bytes. The base address is defined by the CBMA register Addresses shown are in bytes. 6-52 DSP56305 User’s Manual MOTOROLA...

  • Page 201: Figure 6-4 Host Side Registers (universal Bus Mode Address Space)

    Base Address: $6 Host Command Vector Register (HCVR) Base Address: $7 Host Transmit/Slave Receive Data FIFO (HTXR/HRXS) Addresses shown are in words (locations). The base address is defined by eight bits of the CBMA register. MOTOROLA DSP56305 User’s Manual 6-53...

  • Page 202: Hi32 Control Register (hctr)

    HD15-HD0 signals are driven with the two least significant bytes of the HCTR in a read access; HD15-HD0 are written to the two least significant bytes of the HCTR, the most significant portion is zero filled during the HCTR write. 6-54 DSP56305 User’s Manual MOTOROLA...

  • Page 203: Transmit Request Enable (treq) Bit 1

    DMA requests are disabled. If TREQ is set, the host DMA request HDRQ signal will be asserted if HTRQ is set. HIRQ is deasserted (high impedance if HIRD = 0 in the DCTR). The personal hardware reset clears TREQ. MOTOROLA DSP56305 User’s Manual 6-55...

  • Page 204: Receive Request Enable (rreq) Bit 2

    HRRQ, HTRQ Interrupt Requests high impedance Enabled high impedance deasserted HRRQ DMA Request Enabled deasserted HTRQ DMA Request Enabled deasserted HRRQ, HTRQ Host DMA Requests deasserted Enabled high impedance if HIRD = 0 in the DCTR 6-56 DSP56305 User’s Manual MOTOROLA...

  • Page 205: Host Flags (hf2-hf0) Bits 5 And 3, Dma Enable (dmae) Bit 6

    If the HAEN signal is high: • If DMAE is cleared the HI32 cannot be accessed. • If DMAE is set, the HI32 responds to ISA/EISA DMA-type accesses. If DMAE is cleared, the HDRQ signal is deasserted, HIRQ is active. MOTOROLA DSP56305 User’s Manual 6-57...

  • Page 206: Slave Fetch Type (sft) Bit 7

    DTXS; HRRQ is cleared if the HRXS is empty, and set if it contains data to be read by an external host. If the host is not executing a read transaction from the HRXS, the DSP-to-host data path is forced to the reset state and STRQ and HRRQ are cleared. 6-58 DSP56305 User’s Manual MOTOROLA...

  • Page 207

    32-bit word written to the HTXR, the two least significant bytes of the second word read contain the two most significant bytes of the 32-bit word. MOTOROLA DSP56305 User’s Manual 6-59...

  • Page 208

    • If the HTF1-HTF0 value is not equal to the value of the FC1-FC0 bits in the DPMC: PCI transactions that start in the non-data address space (i.e. the PCI address is less than HI32_base_address:$007) should not extend into the data address space. The personal hardware reset clears HTF1-HTF0. 6-60 DSP56305 User’s Manual MOTOROLA...

  • Page 209

    All 32 PCI data bits are written to the HTXR as All HD23-HD0 data are written to the HTXR. two zero-extended 16-bit words. GDB/MDDB GDB/MDDB HI32 HI32 DRXR DRXR HTXR HTXR HDTFC HDTFC PCI bus Host bus MOTOROLA DSP56305 User’s Manual 6-61...

  • Page 210

    The three most significant PCI data bytes are HD15-HD0 are written to the HTXR, left written to the HTXR. aligned, and zero filled. GDB/MDDB GDB/MDDB HI32 HI32 DRXR DRXR HTXR HTXR HDTFC HDTFC PCI bus Host bus 6-62 DSP56305 User’s Manual MOTOROLA...

  • Page 211

    HRXS and output to the HI32 data signals HD15-HD0. • If HRF = $3: The two most significant bytes of the data written to the DTXS is transferred to the HRXS and output to the HI32 data signals HD15-HD0. MOTOROLA DSP56305 User’s Manual 6-63...

  • Page 212: Host Semaphores (hs2-hs0) Bits 16 And 14, Target Wait State Disable (twsd) Bit 19

    Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated. If TWSD is set and the HI32 is in the PCI mode (HM=$1): 6-64 DSP56305 User’s Manual MOTOROLA...

  • Page 213

    The two least significant bytes of two HRXS The three least significant HRXS bytes locations are output. are output to HD23-HD0. GDB/MDDB GDB/MDDB HI32 HI32 DTXS DTXS HRXS HRXS HDTFC HDTFC PCI bus Host bus MOTOROLA DSP56305 User’s Manual 6-65...

  • Page 214

    The three least significant HRXS bytes are The two middle HRXS bytes are output output left aligned and zero filled. to HD15-HD0. GDB/MDDB GDB/MDDB HI32 HI32 DTXS DTXS HRXS HRXS HDTFC HDTFC PCI bus Host bus 6-66 DSP56305 User’s Manual MOTOROLA...

  • Page 215: Bits 31-20, 18-17, 13, 10, And 0

    The personal hardware reset clears TWSD. 6.6.1.10 HCTR Reserved Control Bits 31-20, 18-17, 13, 10, and 0 These bits are reserved for future expansion, they are read as zeros and should be written with zeros for upward compatibility. MOTOROLA DSP56305 User’s Manual 6-67...

  • Page 216: Hi32 Status Register (hstr)

    When in a Universal Bus mode (HM=$2 or $3), the HSTR is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $5. The status bits are described in the following paragraphs. 6-68 DSP56305 User’s Manual MOTOROLA...

  • Page 217: Transmitter Ready (trdy) Bit 0, Host Transmit Data Request (htrq) Bit 1

    HTRQ is cleared. HTRQ may be used to assert the external HIRQ signal if the TREQ bit is set. Regardless of whether the HTRQ host interrupt request is enabled, HTRQ provides valid status so that polling techniques may be used by the host processor. Hardware, software and personal software resets set HTRQ. MOTOROLA DSP56305 User’s Manual 6-69...

  • Page 218: Host Receive Data Request (hrrq) Bit 2, Host Flags (hf5-hf3) Bits 5, 4 And 3

    HINTA signal. HINT is set if the host interrupt A bit is set in the DCTR, and the HINTA signal is driven low. HINT is cleared if the host interrupt A is cleared in the DCTR, and the HINTA signal is driven low. HINT is cleared by a hardware or software reset. 6-70 DSP56305 User’s Manual MOTOROLA...

  • Page 219: Host Request (hreq) Bit 7, Hstr Reserved Status Bits 31-8

    HTRQ = 1 or HRRQ = 1 otherwise cleared The personal hardware reset clears HREQ. 6.6.2.7 HSTR Reserved Status Bits 31-8 These status bits are reserved for future expansion and read as zeros during host read operations. MOTOROLA DSP56305 User’s Manual 6-71...

  • Page 220: Host Command Vector Register (hcvr)

    HD15-HD0 are written to the two least significant bytes of the HCVR, the most significant portion is zero filled during the HCVR write. In PCI mode (HM = $1) memory space transactions, the HCVR is accessed if the PCI address is HI32_base_address: $018. 6-72 DSP56305 User’s Manual MOTOROLA...

  • Page 221: Host Command (hc) Bit 0

    PCI wait cycles, until HC is cleared. • In a Universal Bus mode: In a write transaction to the HCVR, the HI32 slave will deassert HTA, until HC is cleared. The personal software reset clears HC. MOTOROLA DSP56305 User’s Manual 6-73...

  • Page 222: Host Vector (hv6-hv0) Bits 7-1, Host Non-maskable Interrupt (hnmi) Bit 15

    The personal hardware reset clears HNMI. 6.6.3.4 HCVR Reserved Bits 31-16, 14-8 These unused bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros. 6-74 DSP56305 User’s Manual MOTOROLA...

  • Page 223: Host Slave Receive Data Register (hrxs)

    • the HREQ status bit will be set in the HSTR. • the HIRQ signal will be asserted - if DMAE is cleared (in the Universal Bus modes) • the HDRQ signal will be asserted - if DMAE is set (in the Universal Bus modes) MOTOROLA DSP56305 User’s Manual 6-75...

  • Page 224: Host Master Receive Data Register (hrxm), Host Transmit Data Register (htxr)

    The HTXR may be written if the HTRQ bit in the HSTR is set. Data should not be written to the HTXR until HTRQ is set to prevent previous data from being overwritten. Filling the HTXR by host processor writes, clears HTRQ. 6-76 DSP56305 User’s Manual MOTOROLA...

  • Page 225

    In a Universal Bus mode write to the HTXR the HI32 will insert wait states if the HTXR is full (HTRQ = 0). Wait states will be inserted until the data is transferred from the HTXR to the DSP side. Hardware, software and personal software resets empty the HTXR (HTRQ is set). MOTOROLA DSP56305 User’s Manual 6-77...

  • Page 226: Device/vendor Id Configuration Register (cdid/cvid), Status/command Configuration Register (cstr/ccmr)

    The CDID/CVID cannot be accessed by the host when not in the PCI mode (HM≠$1). 6.6.8 Status/Command Configuration Register (CSTR/CCMR) DST1 DST0 FBBC SERE PERR Not implemented, read as zero, should be written zero Reserved, read as zero and should be written zero 6-78 DSP56305 User’s Manual MOTOROLA...

  • Page 227

    FBBC Fast Back-to-Back Capable (hardwired to one) Data Parity Reported 26-25 DST1-DST0 DEVSEL Timing (hardwired to $1) Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error 22-16 reserved MOTOROLA DSP56305 User’s Manual 6-79...

  • Page 228: Memory Space Enable (mse) Bit 1, Bus Master Enable (bm) Bit 2

    PEIE, in the DPCR, is set. The personal hardware reset clears PERE. 6.6.8.4 Wait Cycle Control (WCC) Bit 7 The WCC bit is hardwired to zero, as the HI32 never executes address stepping. 6-80 DSP56305 User’s Manual MOTOROLA...

  • Page 229: System Error Enable (sere) Bit 8, Fast Back-to-back Capable (fbbc) Bit 23

    (HM=$1) and the HI32, as a master device, detects that its transaction is terminated with target-abort, the RTA is set. The RTA bit is cleared when it is written with one by the host processor. The personal hardware reset clears RTA. MOTOROLA DSP56305 User’s Manual 6-81...

  • Page 230: Received Master Abort (rma) Bit 29, Signaled System Error (sse) Bit 30

    They are read by the host processor as zeros. 6.6.8.16 CCMR Not Implemented Bits 9, 5-3 These not implemented bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros. 6-82 DSP56305 User’s Manual MOTOROLA...

  • Page 231

    The RID7-RID0 bits specify the DSP specific identifier (as an extension of Device ID). The CCCR/CRID cannot be accessed by the host when not in the PCI mode (HM≠$1) The contents of CCCR/CRID are hardwired and not affected by any type of reset. MOTOROLA DSP56305 User’s Manual 6-83...

  • Page 232: Header Type (ht7-ht0) Bits 23-16

    Header Type (HT7-HT0) Bits 23-16 The read-only bits HT7-HT0 identify the layout of bytes $10-$3F in the configuration space and also whether or not the device contains multiple functions. This byte is hardwired to the value $00. 6-84 DSP56305 User’s Manual MOTOROLA...

  • Page 233: Latency Timer (lt7-lt0) Bits 15-8, Chty/clat Not Implemented Bits 31-24,7-0

    The personal hardware reset clears LT7-LT0. 6.6.10.3 CHTY/CLAT Not Implemented Bits 31-24,7-0 These not implemented bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros. MOTOROLA DSP56305 User’s Manual 6-85...

  • Page 234: Memory Space Indicator (msi) Bit 0

    Memory Space Indicator (MSI) Bit 0 The MSI determines that CBMA register maps the HI32 into the PCI memory space. The MSI bit is hardwired to zero and is not affected by any type of reset. 6-86 DSP56305 User’s Manual MOTOROLA...

  • Page 235: Memory Space (ms1-ms0) Bits 2 And 1, Pre-fetch (pf) Bit 3

    HA2-HA0 are used to select the HI32 registers on the host side. All reserved register addresses are read as zeros and should be written with zeros for upward compatibility (see Figure 6-4). The personal hardware reset clears GB10-GB3. MOTOROLA DSP56305 User’s Manual 6-87...

  • Page 236

    HI32 has no major requirements for the settings of Latency Timers, these bits are hardwired to zero. IP7-IP0: The Interrupt Signal bits specify which interrupt the device uses. A value of 1 corresponds to PCI INTA. 6-88 DSP56305 User’s Manual MOTOROLA...

  • Page 237: Self Configuration Mode

    Configuration mode (HM2-HM0 = $5) and first write to the DPAR if the first write is a one DSP clock cycle instruction. (e.g. move immediate and move from external memory are more than one clock cycle) MOTOROLA DSP56305 User’s Manual 6-89...

  • Page 238: Self Configuration Procedure For The Pci Mode, Self Configuration Procedure For The Universal Bus Mode

    #$0, x: M_DPAR ; dummy write to location $04 movep #$0, x: M_DPAR ; dummy write to location $08 movep #HIRQ__DURATION, x: M_DPAR ; write CLAT (location $0C) movep #$0, x: M_DPAR ; write CBMA (location $10) 6-90 DSP56305 User’s Manual MOTOROLA...

  • Page 239: Host Port Signals

    HP26 HGNT HAEN disconnected HP27 HREQ disconnected HP28 HSERR HIRQ disconnected HP29 HSTOP disconnected HWR/HRW HP30 HIDSEL disconnected HRD/HDS HP31 HFRAME UNUSED HP32 HCLK UNUSED HP33 disconnected HP34 disconnected HP35 disconnected HD10 HP36 disconnected HD11 MOTOROLA DSP56305 User’s Manual 6-91...

  • Page 240

    5. Should be pulled to Vcc or GND if not used Should be forced or pulled to Vcc or GND if not used Output is high impedance if HRF ≠ $0. Input is disconnected if HTF ≠ $0. 6-92 DSP56305 User’s Manual MOTOROLA...

  • Page 241

    Table 6-18 Host Port Signals - Detailed Description (Sheet 1 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HP7-HP0 HAD15-HAD0 HA10-HA3 PB15-PB0 Address/Data Multiplexed Bus Address Bus Tri-state, bidirectional bus. Input signal. During the first clock cycle of a This bus selects the HI32 register to be accessed.

  • Page 242

    Table 6-18 Host Port Signals - Detailed Description (Sheet 2 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HP18-HP16 HC3/ HBE3 HBE0 HA2-HA0 PB18-PB16 -HC0/ Address Bus Bus Command/Byte Enables Input signal. Tri-state, bidirectional bus. This bus selects the HI32 register to be accessed. During the address phase of a HA10-HA3 select the HI32 and HA2-HA0 select the HBE3...

  • Page 243

    Table 6-18 Host Port Signals - Detailed Description (Sheet 3 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HTRDY HDBEN PB20 Host Data Bus Enable Target Ready Output signal. Sustained tri-state bidirectional signal. Asserted during HI32 accesses. Indicates the target agent’s ability to When asserted the external (optional) data complete the current data phase of transceiver outputs are enabled.

  • Page 244

    Table 6-18 Host Port Signals - Detailed Description (Sheet 4 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HIRDY HDBDR Host Data Bus Direction Initiator Ready Output signal. Sustained tri-state bidirectional HDBDR is driven high on write data signal.

  • Page 245

    Table 6-18 Host Port Signals - Detailed Description (Sheet 5 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HLOCK Lock (Bus Strobe) Sustained tri-state bidirectional Schmitt trigger input signal. Asserted at the start of a bus cycle (for half of a clock cycle) signal.

  • Page 246

    Table 6-18 Host Port Signals - Detailed Description (Sheet 6 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HPERR HDRQ Disconnected Parity Error DMA Request Sustained tri-state bidirectional Output Signal. Used to support ISA/EISA-type DMA data transfers. signal. HDRQ is asserted by the HI32 when a DMA request Used for reporting of data parity (receive and/or transmit) is generated in the HI32.

  • Page 247

    Table 6-18 Host Port Signals - Detailed Description (Sheet 7 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HREQ Disconnected Bus Request Host Transfer Acknowledge Tri-state, Output signal. Tri-state, Output signal. Indicates to the arbiter that the HI32 Used for high speed data transfer between the HI32 and desires use of the bus.

  • Page 248

    Table 6-18 Host Port Signals - Detailed Description (Sheet 8 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HSERR HIRQ Disconnected System Error Host Interrupt Request Active low, open drain output Active low, output signal signal Used by the HI32 to request service from the host Used for reporting address parity processor.

  • Page 249

    Table 6-18 Host Port Signals - Detailed Description (Sheet 9 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HSTOP HWR/HRW Disconnected Stop Host Write/Read-Write Sustained tri-state bidirectional Schmitt trigger input signal. When in the double-strobe mode of the HI32 (HDSM = 0), signal.

  • Page 250

    Table 6-18 Host Port Signals - Detailed Description (Sheet 10 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HIDSEL HRD/HDS Disconnected Initialization Device Select Host Read/Data Strobe Input signal. Schmitt trigger input signal. Used as a chip select in lieu of the When in the double-strobe mode of the HI32 (HDSM = 0), upper 21 address lines during this signal functions as the host read strobe (HRD).

  • Page 251

    Table 6-18 Host Port Signals - Detailed Description (Sheet 11 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HCLK UNUSED Bus Clock Must be forced or pulled up to Vcc. Input signal. Provides timing for all transactions on PCI. All other PCI signals are sampled on the HCLK rising edge.

  • Page 252

    Table 6-18 Host Port Signals - Detailed Description (Sheet 12 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HP48-HP41 HD23-HD16 Disconnected Data Bus Tri-state, bidirectional bus. Used to transfer data between the host processor and the HI32. This bus is released (disconnected) when the HI32 is not selected by HA10-HA0.

  • Page 253

    Table 6-18 Host Port Signals - Detailed Description (Sheet 13 of 13) HI32 HI32 Mode Port Enhanced Universal Universal GPIO HINTA Host Interrupt A Active low, open drain output signal Used by the HI32 to request service from the host processor. HINTA may be connected to an interrupt request signal of a host processor, a control input of external circuitry, or be used as a general purpose open-drain output.

  • Page 254: Interrupt Vectors, Via Programming

    MTRQ (DPSR) Via Programmable Base + 7 Slave Transmit STRQ (DSR) Lowest Via Programmable Base + 8 PCI Master Address MARQ (DPSR) 6.10 VIA PROGRAMMING Below is a table of the DSP56305 via-programmable registers: Register Bits Value Meaning CDID CDID15-CDID0 $1802...

  • Page 255: Examples Of Host To Hi32 Connections

    DSP56305 PCI Bus (target/initiator) (initiator/target) HI32 AD31-AD0 HAD31-HAD0 C3/BE3-C0/BE0 HC3/HBE3-HC0/HBE0 HPAR FRAME HFRAME IRDY HIRDY TRDY HTRDY DEVSEL HDEVSEL STOP HSTOP PERR HPERR SERR HSERR HREQ HGNT IDSEL HIDSEL HRST HCLK LOCK HLOCK INTA HINTA MOTOROLA DSP56305 User’s Manual 6-107...

  • Page 256: Examples Of Host To Hi32 Connections

    HI32 may be externally buffered to drive the current required by the ISA/EISA standard. HI32 inputs should be externally buffered if the other ISA/EISA agents are not “3 Volt friendly” as defined in the PCI specifications. 6-108 DSP56305 User’s Manual MOTOROLA...

  • Page 257: Figure 6-7 Example Of Connection To Dsp56300 Core Port A Bus

    If the HI32’s DSP and the host DSP use the same EXTAL clock, the HI32 can operate synchronously at its maximum throughput of three clock cycles/word (e.g. for a 66MHz clock the HI32 throughput is 22 Mwords/sec = 66 Mbytes/sec) MOTOROLA DSP56305 User’s Manual 6-109...

  • Page 258

    HOST INTERFACE (HI32) EXAMPLES OF HOST TO HI32 CONNECTIONS 6-110 DSP56305 User’s Manual MOTOROLA...

  • Page 259

    SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) MOTOROLA DSP56305 User’s Manual...

  • Page 260: Essi Enhancements, Introduction

    Operating Modes ........7-42 GPIO/ESSI Selection and GPIO Usage ....7-52 DSP56305 User’s Manual MOTOROLA...

  • Page 261: Essi Enhancements

    There are two independent and identical Enhanced Synchronous Serial Interfaces in the DSP56305: ESSI0 and ESSI1. For the sake of simplicity, a single generic ESSI is described. Each ESSI can be accessed through a port, as indicated in Figure 7-2. Any unused ESSI pins may be used as GPIO pins.

  • Page 262: Essi Data And Control Signals, Serial Transmit Data Signal (std)

    STD signal does not assume a high-impedance state. The STD signal may be programmed as a General Purpose Input/Output (GPIO) signal (P5) when the ESSI STD function is not being used. DSP56305 User’s Manual MOTOROLA...

  • Page 263: Serial Receive Data Signal (srd)

    GDB DDB RCLK RX SHIFT REG RSMA RSMB TCLK TSMA TX0 SHIFT REG TSMB TX1 SHIFT REG TX2 SHIFT REG SSISR Interrupts Clock/Frame Sync Generators and Control Logic AA0678 Figure 7-1 ESSI Block Diagram MOTOROLA DSP56305 User’s Manual...

  • Page 264: Serial Clock (sck)

    DSP system clock, the external ESSI clock frequency must not exceed /3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT core cycles. 2. The internally sourced ESSI clock frequency must not exceed F core DSP56305 User’s Manual MOTOROLA...

  • Page 265

    Table 7-1 ESSI Clock Sources R Clock T Clock SCKD SCD0 Clock TX Clock Out Source Source Asynchronous EXT, SC0 — EXT, SCK — EXT, SCK — EXT, SC0 — Synchronous EXT, SCK — EXT, SCK — MOTOROLA DSP56305 User’s Manual...

  • Page 266: Serial Control Signal (sc0)

    If SC0 is configured as a serial flag signal, its direction is determined by the Serial Control Direction 0 (SCD0) bit in the ESSI Control Register B (CRB). When configured as an output, its direction is determined by the value of the serial Output Flag 0 (OF0) bit in the CRB. DSP56305 User’s Manual MOTOROLA...

  • Page 267

    (STD and SC1). SC0 may be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being used. Note: The ESSI can operate with more than one active transmitter only in Synchronous mode. MOTOROLA DSP56305 User’s Manual...

  • Page 268: Serial Control Signal (sc1)

    SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data signals (STD and SC0). SC1 may be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being used. 7-10 DSP56305 User’s Manual MOTOROLA...

  • Page 269

    Flag 1 Flag 1 TD0 Drive SCn1 pin is... Frame Sync Frame Sync Enable Out Note: “n” in SCn1 is ESSI (0 or 1) TDm = Transmit Data Signal m AA1456 Figure 7-4 SCn1 Pin Configuration MOTOROLA DSP56305 User’s Manual 7-11...

  • Page 270: Serial Control Signal (sc2)

    SCD2 SCD2 direction? Input Output Input Output TX/RX TX/RX SCn2 pin is... Frame Sync Frame Sync Frame Sync Frame Sync Note: “n” in SCn2 is ESSI (0 or 1) AA1459 Figure 7-5 SCn2 Pin Configuration 7-12 DSP56305 User’s Manual MOTOROLA...

  • Page 271: Essi Programming Model

    Figure 7-6 ESSI Control Register A (CRA) (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 REIE TEIE RLIE TLIE AA0858 Figure 7-7 ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6) AA0859 Figure 7-8 ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) MOTOROLA DSP56305 User’s Manual 7-13...

  • Page 272

    The Transmit and Receive Slot Mask registers are each 24-bit, of which only the lower 16 bits are significant, so TSMA/TSMB and RSMA/RSMB can function as the bottom and top halves of a 32-bit register. 7-14 DSP56305 User’s Manual MOTOROLA...

  • Page 273: Essi Control Register A (cra)

    (see Figure 7-13). Note: This definition is reversed from that of the 560xx SSI. The maximum allowed internally generated bit clock frequency is the DSP56305 internal clock frequency divided by 4 (F /4); the minimum possible internally generated bit...

  • Page 274

    This can occur if one or both of these clocks are externally sourced. If this is the case, then the RX and TX frame clock rates will differ accordingly. DC[4:0] are cleared by hardware and software reset. 7-16 DSP56305 User’s Manual MOTOROLA...

  • Page 275: Normal Mode (mod = 0), Network Mode (mod = 1; Dc ≠ 00000)

    ESSI transmit register, and one word is shifted in (width set by CRA(WL[2:0])) on the ESSI serial input pin as a result of a receive frame sync being input to the DSP. For overview information about On-demand mode, see Section 7.5.3.3. MOTOROLA DSP56305 User’s Manual 7-17...

  • Page 276

    Note: If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of 24- or 32-bit words leads to unpredictable results. 7-18 DSP56305 User’s Manual MOTOROLA...

  • Page 277

    (TE2 = 0), and the SC1 signal is configured as output (SCD1 = 1), then the SC1 signal is the serial I/O flag. The reset value is cleared. 7.4.1.9 Reserved CRA Bit 23 This bit is reserved. It is read as 0 and should be written with 0. MOTOROLA DSP56305 User’s Manual 7-19...

  • Page 278: Essi Control Register B (crb), Serial Output Flag 0 (of0) Crb Bit 0

    Data present in bit OF0 is written to SC0 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode. Bit OF0 is cleared by a hardware reset signal or by a software reset instruction. 7-20 DSP56305 User’s Manual MOTOROLA...

  • Page 279: Serial Output Flag 1 (of1) Crb Bit 1

    Flag 1 Flag 0 Bit Number SCKD SCD2 SCD1 SCD0 SCKn SCn2 SCn1 SCn0 Clock F.S. F.S. Clock Asynchronous Mode (SYN = 0) AA0849 Figure 7-15 ESSI Pin Configuration for Clocks, Frame Syncs, and Flags MOTOROLA DSP56305 User’s Manual 7-21...

  • Page 280: Serial Control Direction 1 (scd1) Crb Bit 3

    7.4.2.7 Frame Sync Length FSL[1:0] CRB Bits 8-7 These bits select the length of frame sync to be generated or recognized (see Figure 7-16). The meaning of the FSL[1:0] values is described in Table 7-3. 7-22 DSP56305 User’s Manual MOTOROLA...

  • Page 281: Frame Sync Relative Timing (fsr) Crb Bit 9

    When FSP is set, the frame sync signal polarity is negative (i.e., the frame start is indicated by the frame sync signal going low). Either a hardware reset signal or a software reset instruction clears FRB. MOTOROLA DSP56305 User’s Manual 7-23...

  • Page 282

    Synchronous mode and the transmit and receive sections use common clock and frame sync signals. Only in the Synchronous mode can more than one transmitter can be enabled. Either a hardware reset signal or a software reset instruction clears SYN. 7-24 DSP56305 User’s Manual MOTOROLA...

  • Page 283: Figure 7-16 Crb Fsl[1:0] Bit Operation

    Data Mixed Frame Length: FSL[1:0] = 11, (SYN = 0) Serial Clock RX Frame SYNC RX Serial Data Data Data TX Frame SYNC TX Serial Data Data Data AA0681 Figure 7-16 CRB FSL[1:0] Bit Operation MOTOROLA DSP56305 User’s Manual 7-25...

  • Page 284: Essi Mode Select (mod) Crb Bit 13, Figure 7-17 Crb Syn Bit Operation

    External Clock External Frame SYNC Internal Clock Internal Frame SYNC ESSI Bit Clock Clock Frame SYNC Receiver NOTE: Transmitter and receiver may have the same clock frame syncs. AA0682 Figure 7-17 CRB SYN Bit Operation 7-26 DSP56305 User’s Manual MOTOROLA...

  • Page 285

    Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model MOTOROLA DSP56305 User’s Manual 7-27...

  • Page 286: From The Essi, Essi Transmit 2 Enable (te2) Crb Bit 14

    TE2 bit can be left enabled. The TE2 bit is cleared by either a hardware reset signal or a software reset instruction. The setting of the TE2 bit does not affect the generation of frame sync or Note: output flags. 7-28 DSP56305 User’s Manual MOTOROLA...

  • Page 287: Essi Transmit 1 Enable (te1) Crb Bit 15

    TE1 bit can be left enabled. The TE1 bit is cleared by either a hardware reset signal or a software reset instruction. The setting of the TE1 bit does not affect the generation of frame sync or Note: output flags. MOTOROLA DSP56305 User’s Manual 7-29...

  • Page 288: Essi Transmit 0 Enable (te0) Crb Bit 16

    The On-demand mode transmit enable sequence can be the same as the Normal mode, or TE0 can be left enabled. Note: Transmitter 0 is the only transmitter that can operate in Asynchronous mode (SYN = 0). TE0 does not affect the generation of frame sync or output flags. 7-30 DSP56305 User’s Manual MOTOROLA...

  • Page 289

    ESSI Programming Model Table 7-4 Mode and Signal Definition Table Control Bits ESSI Signals CLKR CLKT CLKR CLKT TTD0 F0/U F1/U F0/U F1/U F0/U F0/U F1/T0DE/U F1/T0DE/U F0/U F1/T0DE/U F0/U F1/T0DE/U F0/U F0/U F1/T0DE/U F1/T0DE/U MOTOROLA DSP56305 User’s Manual 7-31...

  • Page 290: Essi Receive Enable (re) Crb Bit 17

    The receiver remains disabled until the beginning of the next data frame. RE is cleared by either a hardware reset signal or a software reset instruction. Note: The RE bit value does not affect frame sync generation. 7-32 DSP56305 User’s Manual MOTOROLA...

  • Page 291: Essi Transmit Interrupt Enable (tie) Crb Bit 18

    Section 7.5.2. RLIE is cleared by either a hardware reset signal or a software reset instruction. RLIE is disabled when the ESSI is in On-demand mode (DC [4:0]= 00000, in CRA Bits 16-12). MOTOROLA DSP56305 User’s Manual 7-33...

  • Page 292: Essi Status Register (ssisr), Serial Input Flag 0 (if0) Ssisr Bit 0

    The IF0 bit is updated with this data when the data in the Receive Shift Register is transferred into the Receive Data Register. If it is not enabled, the IF0 bit is cleared. Hardware, software, ESSI individual, and stop reset clear the IF0 bit. 7-34 DSP56305 User’s Manual MOTOROLA...

  • Page 293: Serial Input Flag 1 (if1) Ssisr Bit 1

    RFS is cleared by hardware, software, ESSI individual, or stop reset. Note: In Normal mode, RFS is always read as 1 when reading data because there is only one time slot per frame, the ‘frame sync’ time slot. MOTOROLA DSP56305 User’s Manual 7-35...

  • Page 294: Transmitter Underrun Error Flag (tue) Ssisr Bit 4

    Receive Data Register. The RDF bit is cleared when the DSP reads the Receive Data Register. If RIE is set, a DSP receive data interrupt request is issued when RDF is set. Hardware, software, ESSI individual, and stop reset clear the RDF bit. 7-36 DSP56305 User’s Manual MOTOROLA...

  • Page 295: Figure 7-19 Essi Data Path Programming Model (shfd = 0)

    24-bit Data NOTES: (b) Transmit Registers •Data is transmitted MSB first ifSHFD = 0 •24-bit fractional format (ALC = 0) •32-bit mode is not shown AA0686 Figure 7-19 ESSI Data Path Programming Model (SHFD = 0) MOTOROLA DSP56305 User’s Manual 7-37...

  • Page 296: Figure 7-20 Essi Data Path Programming Model (shfd = 1)

    NOTES: (b) Transmit Registers •Data is received MSB first if SHFD = 0 •24-bit fractional format (ALC = 0) •32-bit mode is not shown AA0687 Figure 7-20 ESSI Data Path Programming Model (SHFD = 1) 7-38 DSP56305 User’s Manual MOTOROLA...

  • Page 297: Essi Receive Shift Register, Essi Receive Data Register (rx), Essi Transmit Shift Registers

    MSB is Bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the SHFD bit is set. MOTOROLA DSP56305 User’s Manual 7-39...

  • Page 298: Essi Transmit Data Registers, Essi Time Slot Register (tsr), Transmit Slot Mask Registers (tsma, Tsmb)

    TSM. Bit k in TSM (TSMk) is an enable/disable control bit for transmission in slot number K. When TSMk is cleared, all the transmit data signals of the enabled transmitters are tri-stated during transmit time slot number K. The data is still 7-40 DSP56305 User’s Manual MOTOROLA...

  • Page 299: Receive Slot Mask Registers (rsma, Rsmb)

    RDF flag is set. Changing the bits in the RSM affects the next frame transmission. The frame currently being received is not affected by the new RSM value. If the RSM is read, it shows the current value. MOTOROLA DSP56305 User’s Manual 7-41...

  • Page 300: Essi Initialization, Operating Modes

    DMA accesses to the data registers of the ESSI are not valid and data read is undefined. To ensure proper operation of the ESSI, use an ESSI individual reset when changing the ESSI Control Registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE). 7-42 DSP56305 User’s Manual MOTOROLA...

  • Page 301

    (either internally or externally generated) only when the Receive Enable (RE) bit is set. • Data will be transmitted after the occurrence of a frame sync signal (either internally or externally generated) only when the Transmitter Enable (TE[2:0]) bit is set. MOTOROLA DSP56305 User’s Manual 7-43...

  • Page 302: Essi Exceptions, Essi Exception Types

    This exception sets the TUE bit. The TUE bit is cleared by first reading the SSISR and then writing to all the Transmit Data Registers of the enabled transmitters, or by writing to the TSR to clear the pending interrupt. 7-44 DSP56305 User’s Manual MOTOROLA...

  • Page 303: Exception Configuration

    Write data to all enabled transmit registers. TX00 c. Enable peripheral interrupt-generating function. CRB(TE0) d. Enable specific peripheral interrupt. CRB0(TIE) e. Enable peripheral and associated signals. PCRC(PC5:0) f. Unmask interrupts at global level. SR(I1:0) MOTOROLA DSP56305 User’s Manual 7-45...

  • Page 304

    (the event will not be queued in this case). 5. If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts, step 2f should be done last. 7-46 DSP56305 User’s Manual MOTOROLA...

  • Page 305: Normal Mode (crb(mod) = 0), Operating Modes, Network Mode (crb(mod) = 1; Cra(dc) ≠ 00000)

    24 ESSI clock periods (“bit times”). An edge on the receive or transmit frame sync signal (rising or falling edge, but never both) indicates the beginning of a new data frame. MOTOROLA DSP56305 User’s Manual 7-47...

  • Page 306

    Various solutions are possible, such as multiple DMA channels, software counters, or input/output buffers with a known data interleaving scheme. Details on programming the ESSI in network mode are given in subsequent sections. 7-48 DSP56305 User’s Manual MOTOROLA...

  • Page 307: On-demand Mode (crb(mod) = 1, Dc = 00000), Synchronous/asynchronous Operating Modes

    The ESSI receive timing may be independent of the transmit timing. In the Normal and Network modes, the receive channel may be asynchronous with respect to the transmit channel(s); i.e., the receive clock rate may not match the transmit clock rate. As a result, MOTOROLA DSP56305 User’s Manual 7-49...

  • Page 308: Frame Sync Settings, Frame Sync Signal Format, Frame Sync Length For Multiple Devices

    • If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift registers, and telecommunication Pulse Code Modulation (PCM) serial I/O.

  • Page 309: Frame Sync Polarity, Selecting The Bit Shift Order For The Transmitter

    Transmit Shift Register MSB first. • If the SHFD bit is set, data is shifted into the Receive Shift Register LSB first and shifted out of the Transmit Shift Register LSB first. MOTOROLA DSP56305 User’s Manual 7-51...

  • Page 310: Essi Flag Usage, Gpio/essi Selection And Gpio Usage

    The OF[1:0] values can be set directly by software. This allows the DSP56305 to control data transmission by indirectly controlling the value of the SC[1:0] flags.

  • Page 311: Port Control Register (pcr), Figure 7-22 Gpio/essi Port Organization, Figure 7-23 Port Control Register (pcr)

    0 = GPIO, 1 = ESSI PCRC: ESSI0, X:$FFFFBF STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PCRD: ESSI1, X:$FFFFAF Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0688 Figure 7-23 Port Control Register (PCR) MOTOROLA DSP56305 User’s Manual 7-53...

  • Page 312: Port Direction Register (prr), Figure 7-24 Port Direction Register (prr)

    The following table describes the port signal configurations. Table 7-5 Port Control Register and Port Direction Register Bits Functionality PC[i] PDC[i] Port Signal[i] Function ESSI GPIO input GPIO output Note: X: The signal setting is irrelevant to Port Signal[i] function. 7-54 DSP56305 User’s Manual MOTOROLA...

  • Page 313: Port Data Register (pdr), Figure 7-25 Port Data Register (pdr)

    Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0690 Figure 7-25 Port Data Register (PDR) Note: Either a hardware reset signal or a software reset instruction clear all PDR bits. MOTOROLA DSP56305 User’s Manual 7-55...

  • Page 314

    Enhanced Synchronous Serial Interface (ESSI) GPIO/ESSI Selection and GPIO Usage 7-56 DSP56305 User’s Manual MOTOROLA...

  • Page 315: Section 8 Serial Communication Interface (sci)

    SECTION 8 SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA DSP56305 User’s Manual...

  • Page 316

    Operating Modes ........8-21 GPIO Signals and Registers ......8-27 DSP56305 User’s Manual MOTOROLA...

  • Page 317: Sci I/o Signals, Introduction

    80 MHz clock). The asynchronous protocols supported by the SCI include a Multidrop mode for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. This mode allows the DSP56305 to share a single serial line efficiently with other peripherals.

  • Page 318: Receive Data (rxd), Transmit Data (txd), Sci Serial Clock (sclk)

    TXD, since the clock does not need to be transmitted in the Asynchronous mode. Because SCLK is independent of SCI data I/O, there is no connection between programming the PE2 signal as SCLK and data coming out the TXD signal. DSP56305 User’s Manual MOTOROLA...

  • Page 319: Sci Programming Model

    – SCI Transmit Data Registers (STX) in Figure 8-8 – SCI Transmit Data Address Register (STXA) in Figure 8-8 The SCI also contains GPIO functionality, as described in Section 8.5. The following paragraphs describe each bit in the programming model. MOTOROLA DSP56305 User’s Manual...

  • Page 320: Figure 8-1 Sci Control Register (scr), Figure 8-2 Sci Status Register (ssr)

    Figure 8-1 SCI Control Register (SCR) IDLE RDRF TDRE TRNE AA0855 Figure 8-2 SCI Status Register (SSR) CD11 CD10 Reserved bit - read as 0 should be written with 0 for future compatibility AA0856 Figure 8-3 SCI Clock Control Register (SCCR) DSP56305 User’s Manual MOTOROLA...

  • Page 321: Figure 8-4 Sci Data Word Formats (ssftd=0)

    0 = Data Byte 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691a Figure 8-4 SCI Data Word Formats (SSFTD=0) MOTOROLA DSP56305 User’s Manual...

  • Page 322: Figure 8-5 Sci Data Word Formats (ssftd=1)

    0 = Data Byte 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691b Figure 8-5 SCI Data Word Formats (SSFTD=1) DSP56305 User’s Manual MOTOROLA...

  • Page 323: Sci Control Register (scr), Word Select (wds[0:2]) Scr Bits 0-2

    The Synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0. MOTOROLA DSP56305 User’s Manual...

  • Page 324: Sci Shift Direction (ssftd) Scr Bit 3, Send Break (sbk) Scr Bit 4

    WAKE is cleared by hardware and software reset. 8-10 DSP56305 User’s Manual MOTOROLA...

  • Page 325: Receiver Wakeup Enable (rwu) Scr Bit 6, Wired-or Mode Select (woms) Scr Bit 7

    If RE is cleared while a character is being received, the reception of the character is completed before the receiver is disabled. RE does not inhibit RDRF or receive interrupts. RE is cleared by hardware and software reset. MOTOROLA DSP56305 User’s Manual 8-11...

  • Page 326: Transmitter Enable (te) Scr Bit 9, Idle Line Interrupt Enable (ilie) Scr Bit 10

    The results are as follows: 1. The IDLE bit shows the real status of the receive line at all times. 2. An idle interrupt is generated once for each idle state, no matter how long the idle state lasts. 8-12 DSP56305 User’s Manual MOTOROLA...

  • Page 327: Sci Receive Interrupt Enable (rie) Scr Bit 11

    This bit is cleared by hardware and software reset. To ensure proper operation of the timer, STIR must not be changed during timer operation (i.e., if TMIE = 1). MOTOROLA DSP56305 User’s Manual 8-13...

  • Page 328: Sci Clock Polarity (sckp) Scr Bit 15, Reie) Scr Bit 16, Sci Status Register (ssr)

    The TDRE flag bit is set when the SCI Transmit Data Register is empty. When TDRE is set, new data can be written to one of the SCI Transmit Data Registers (STX) or the Transmit Data Address Register (STXA). TDRE is cleared when the SCI Transmit Data 8-14 DSP56305 User’s Manual MOTOROLA...

  • Page 329: Receive Data Register Full (rdrf) Ssr Bit 2, Idle Line Flag (idle) Ssr Bit 3

    OR is cleared when the SCI status Register (SSR) is read, followed by a read of SRX. The OR bit clears the FE and PE bits—that is, overrun error has higher priority than FE or PE. OR is cleared by the hardware, software, SCI individual, and stop resets. MOTOROLA DSP56305 User’s Manual 8-15...

  • Page 330: Parity Error (pe) Ssr Bit 5, Framing Error Flag (fe) Ssr Bit 6

    R8 is set for addresses and is cleared for data. R8 is not affected by reading the SRX or SSR. The hardware, software, SCI individual, and stop resets clear R8. 8-16 DSP56305 User’s Manual MOTOROLA...

  • Page 331: Sci Clock Control Register (sccr)

    SCI peripheral block is the oscillator frequency divided by 4. With an 80 MHz DSP56305 processor, this gives a maximum data rate of 1.25 Mbps for asynchronous data and 10.0 Mbps for synchronous data. These maximum rates are the same for internally or externally supplied clocks.

  • Page 332: Clock Divider (cd[11:0]) Sccr Bits 11–0, Clock Out Divider (cod) Sccr Bit 12

    The SCP bit selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock divider. The output of the prescaler is further divided by 2 to form the SCI clock. Hardware and software reset clear SCP. 8-18 DSP56305 User’s Manual MOTOROLA...

  • Page 333: Receive Clock Mode Source Bit (rcm) Sccr Bit 14, Figure 8-7 Sci Baud Rate Generator

    SCKP = 1 – 64 × (7 × SCP + 1) × CD + 1) where: SCP = 0 or 1 CD = $000 to $FFF TO SCLK AA0693 Figure 8-7 SCI Baud Rate Generator MOTOROLA DSP56305 User’s Manual 8-19...

  • Page 334: Transmit Clock Source Bit (tcm) Sccr Bit 15, Sci Data Registers

    SCI Transmit Data Address Register (Write Only) STXA Note: 1. Bytes are masked on the fly. 2. STX is the same register decoded at four different addresses. (b) Transmit Data Register AA0694 Figure 8-8 SCI Programming Model - Data Registers 8-20 DSP56305 User’s Manual MOTOROLA...

  • Page 335: Sci Receive Registers (srx), Sci Transmit Registers

    (the address bit) be set. When STXA is written, the data from the low byte on the data bus is stored in it. The address data bit is cleared in the 11-bit Asynchronous Multidrop mode when any of MOTOROLA DSP56305 User’s Manual 8-21...

  • Page 336

    If the user reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 Family Manual, Appendix B, “Polling a Peripheral Device for Write,” for further details. 8-22 DSP56305 User’s Manual MOTOROLA...

  • Page 337

    • 11-bit Multidrop Asynchronous (1 start, 8 data, 1 data type, 1 stop) This mode is used for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. It allows the DSP56305 to share a single serial line efficiently with other peripherals.

  • Page 338: Sci After Reset

    Executing the STOP instruction halts operation of the SCI until the DSP is restarted, causing the SSR to be reset. No other SCI registers are affected by the STOP instruction. Table 8-3 illustrates how each type of reset affects each register in the SCI. 8-24 DSP56305 User’s Manual MOTOROLA...

  • Page 339

    — TMIE — — — — — — ILIE — — — — — — WOMS — — — — WAKE — — — — SSFTD — — WDS[2:0] 2–0 — — IDLE RDRF TDRE MOTOROLA DSP56305 User’s Manual 8-25...

  • Page 340

    IR—Individual reset is caused by clearing PCRE (bits 0–2) (configured for ST—Stop reset is caused by executing the STOP instruction. 1—The bit is set during this reset. 0—The bit is cleared during this reset. — — The bit is not changed during this reset 8-26 DSP56305 User’s Manual MOTOROLA...

  • Page 341: Sci Initialization, Sci Initialization Example

    The SCI transmit request is serviced by a DMA channel if it is programmed to service the SCI transmitter. 5. Enable the transmitters (TE = 1) and receiver (RE = 1), according to usage. MOTOROLA DSP56305 User’s Manual 8-27...

  • Page 342: Preamble, Break, And Data Transmission Priority

    3. Data for transmission available (TDRE is cleared.) After the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order: 1. Preamble 2. Break 3. Data Available 8-28 DSP56305 User’s Manual MOTOROLA...

  • Page 343: Sci Exceptions, Gpio Signals And Registers, Port E Control Register (pcre)

    PC[2:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the corresponding port signal is configured as a SCI signal. When a PC[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. MOTOROLA DSP56305 User’s Manual 8-29...

  • Page 344: Port E Direction Register (prre), Figure 8-9 Port E Control Register (pcre)

    Direction Control Bits: 1 = Output 0 = Input Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility AA0696 Figure 8-10 Port E Direction Register (PRRE) Note: Hardware and software reset clear all PRRE bits. 8-30 DSP56305 User’s Manual MOTOROLA...

  • Page 345: Port E Data Register (pdre), Figure 8-11 Port E Data Register (pdre)

    GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal. Data Value Bits Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility AA0697 Figure 8-11 Port E Data Register (PDRE) Note: Hardware and software reset clear all PDRE bits. MOTOROLA DSP56305 User’s Manual 8-31...

  • Page 346

    Serial Communication Interface (SCI) GPIO Signals and Registers 8-32 DSP56305 User’s Manual MOTOROLA...

  • Page 347: Section 9 Timer/event Counter, Timer/event Counter

    SECTION 9 TIMER/EVENT COUNTER MOTOROLA DSP56305 User’s Manual...

  • Page 348: Table Of Contents

    Timer Architecture ........9-7 Timer Modes of Operation ......9-18 DSP56305 User’s Manual MOTOROLA...

  • Page 349: Introduction To The Timer/event Counter, Timer/event Counter Architecture

    Timer/Event Counter Introduction to the Timer/Event Counter INTRODUCTION TO THE TIMER/EVENT COUNTER This section describes the internal Timer/Event Counter module (TEC) in the DSP56305. The TEC comprises: • a 21-bit prescaler counter • a 24-bit Timer Prescaler Load Register (TPLR) •...

  • Page 350: Timer/event Counter Block Diagram, Timer/event Counter Programming Model, Figure 9-1 Timer/event Counter Block Diagram

    Timer/Event Counter Programming Model The programming model for the TEC consists of the 21-bit prescaler counter, the 24-bit Timer Prescaler Load Register (TPLR), and the 24-bit Timer Prescaler Count Register (TPCR). Figure 9-3 shows the TEC programming model. DSP56305 User’s Manual MOTOROLA...

  • Page 351: Prescaler Counter, Timer Prescaler Load Register (tplr), Figure 9-2 Timer/event Counter Programming Model

    (see Figure ). PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 PL11 PL10 — reserved, read as 0, should be written with 0 for future compatibility Figure 9-3 Timer Prescaler Load Register (TPLR) MOTOROLA DSP56305 User’s Manual...

  • Page 352: Prescaler Preload Value Pl[20:0] — Tplr Bits 20-0, Prescaler Source Ps[1:0] — Tplr Bits 22-21

    If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be less than the DSP56305 internal operating frequency divided by 4 (CLK/4).

  • Page 353: Timer Prescaler Count Register (tpcr), Prescaler Counter Value Pc[20:0] — Tpcr Bits 20-0

    These reserved bits are read as 0 and should be written with 0 for future compatibility. TIMER ARCHITECTURE The DSP56305 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers.

  • Page 354

    TIOn becomes the timer pulse. Timer modes are controlled by the TC[3:0] bits of the Timer Control/Status Register (TCSR). For a listing of the timer modes, see Section 9.4. For a description of their operation, see Section 9.4.1. DSP56305 User’s Manual MOTOROLA...

  • Page 355: Timer Block Diagram, Timer Programming Model, Figure 9-5 Timer Block Diagram

    Control and Status Register (TCSR), a 24-bit write-only Timer Load Register (TLR), a 24-bit read/write Timer Compare Register (TCPR), and a 24-bit read-only Timer Count Register (TCR). The timers are functionally identical. Figure 9-6 shows the timer programming model. MOTOROLA DSP56305 User’s Manual...

  • Page 356: Timer Control/status Register (tcsr), Figure 9-6 Timer Programming Model

    Figure 9-6 Timer Programming Model 9.3.3 Timer Control/Status Register (TCSR) The Timer Control/Status Register (TCSR) is a 24-bit read/write register controlling the timer and reflecting its status. The control and status bits are described below. 9-10 DSP56305 User’s Manual MOTOROLA...

  • Page 357: Timer Enable (te) — Tcsr Bit 0, Toie) — Tcsr Bit 1

    The TC bits are cleared by a hardware RESET signal or a software RESET instruction. If the clock is external, the counter is incremented by the transitions on the Note: TIO signal. The DSP56305 synchronizes the external clock to the internal clock. MOTOROLA DSP56305 User’s Manual...

  • Page 358

    Output Internal Watchdog Toggle Output Internal Reserved — — Reserved — — Reserved — — Reserved — — Reserved — — Note: The GPIO function is enabled only if the TC[3:0] bits are all 0. 9-12 DSP56305 User’s Manual MOTOROLA...

  • Page 359: Inverter (inv) — Tcsr Bit 8

    Width of the low — — input pulse is input pulse is measured. measured. Period is Period is — — measured measured between the between the rising edges of falling edges of the input signal. the input signal. MOTOROLA DSP56305 User’s Manual 9-13...

  • Page 360: Timer Reload Mode (trm) — Tcsr Bit 9

    • In Timer (0–3) and Watchdog (9–10) modes, the counter is reloaded each time after it reaches the value contained by the TCPR. Initially, the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received. 9-14 DSP56305 User’s Manual MOTOROLA...

  • Page 361: Direction (dir) — Tcsr Bit 11, Data Input (di) — Tcsr Bit 12

    DO bit is written directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect. The DO bit is cleared by a hardware RESET signal or a software RESET instruction. MOTOROLA DSP56305 User’s Manual 9-15...

  • Page 362: Prescaler Clock Enable (pce) — Tcsr Bit 15

    0 to the other flag. 9.3.3.13 Reserved Bits — TCSR Bits 3, 10, 14, 16-19, 22, 23 These reserved bits are read as 0 and should be written with 0 for future compatibility. 9-16 DSP56305 User’s Manual MOTOROLA...

  • Page 363: Timer Load Register (tlr), Timer Compare Register (tcpr), Timer Count Register (tcr)

    When the timer is in Measurement modes, the TIO signal is used for the input signal. MOTOROLA DSP56305 User’s Manual 9-17...

  • Page 364: Timer Modes Of Operation

    (when the TE bit (TCSR Bit 0) is cleared). To enable the timer, set the TE bit. If the TE bit is cleared, the TIO (timer) signal acts as a GPIO signal. 9-18 DSP56305 User’s Manual MOTOROLA...

  • Page 365: Timer Modes, Timer Gpio (mode 0)

    TOF bit (TCSR Bit 20) is set; if the TOIE bit (TCSR Bit 1) is set, an overflow interrupt is generated and the counter is reloaded with the TLR value. The counter contents can be read at any time by reading the TCR. MOTOROLA DSP56305 User’s Manual 9-19...

  • Page 366: Timer Pulse (mode 1)

    The TIO bit polarity is dependent on the INV bit value. When TE is set, the TIO signal output value is put equal to the INV bit value to guarantee the first signal transition is correct. 9-20 DSP56305 User’s Manual MOTOROLA...

  • Page 367: Timer Toggle (mode 2)

    The TIO bit polarity is dependent on the INV bit value. When TE is set, the TIO signal output value is put equal to the INV bit value to guarantee the first signal transition is correct. MOTOROLA DSP56305 User’s Manual 9-21...

  • Page 368: Timer Event Counter (mode 3)

    Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock and its frequency must be less than the DSP56305 internal operating frequency divided by four (i.e., CLK/4).

  • Page 369: Signal Measurement Modes, Measurement Accuracy, Measurement Input Width (mode 4)

    (as determined by the INV bit) occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56305 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.

  • Page 370: Measurement Input Period (mode 5)

    TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56305 clock divided by two (CLK/2), or the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 371: Measurement Capture (mode 6)

    TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56305 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 372: Pulse Width Modulation (pwm, Mode 7)

    Set the TE bit to clear the counter and enable the timer. When first timer clock is received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock increments the counter.

  • Page 373: Watchdog Modes, Watchdog Pulse (mode 9)

    TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter.

  • Page 374: Watchdog Toggle (mode 10)

    TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO signal is set to the value of the INV bit.

  • Page 375: Reserved Modes, Special Cases, Timer Behavior During Wait, Timer Behavior During Stop, Dma Trigger

    9.4.6.1 Timer Behavior during Wait Timer clocks are active during the execution of the WAIT instruction, and timer activity is undisturbed. If a timer interrupt is generated, the DSP56305 leaves the Wait state and services the interrupt. 9.4.6.2 Timer Behavior during Stop During the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and the TIO signals are disconnected.

  • Page 376

    Timer/Event Counter Timer Modes of Operation 9-30 DSP56305 User’s Manual MOTOROLA...

  • Page 377: Section 10 On-chip Emulation Module, On-chip Emulation Module

    SECTION 10 ON-CHIP EMULATION MODULE MOTOROLA DSP56305 User’s Manual 10-1...

  • Page 378: Table Of Contents

    Examples of Using the OnCE ......10-24 10.13 Examples of JTAG and OnCE interaction ....10-29 10-2 DSP56305 User’s Manual MOTOROLA...

  • Page 379: Once Module Signals, Introduction, Figure 10-1 Once Module Block Diagram

    The JTAG signals TCK, TDI, and TDO are used to shift data and instructions in and out. See JTAG Signals on page 11-5 for the description of the JTAG signals. To facilitate emulation-specific functions, one additional signal, called DE, is provided on the DSP56305. MOTOROLA DSP56305 User’s Manual 10-3...

  • Page 380: Debug Event (de), Figure 10-2 Once Module Multiprocessor Configuration, Debug Event (de)

    Figure 10-2 OnCE Module Multiprocessor Configuration The user can stop all the devices in the system when one of the devices enters the Debug mode. The user can also stop all the devices synchronously by asserting the DE line. 10-4 DSP56305 User’s Manual MOTOROLA...

  • Page 381: Once Controller, Once Command Register (ocr), Figure 10-3 Once Controller Block Diagram

    TDI signal. It holds the 8-bit commands to be used as input for the OnCE Decoder. The OCR is shown in Figure 10-4. OnCE Command Register RS4 RS3 RS2 RS1 RS0 Reset = $00 Write Only AA0106 Figure 10-4 OnCE Command Register MOTOROLA DSP56305 User’s Manual 10-5...

  • Page 382: Register Select (rs4–rs0) Bits 0–4, Exit Command (ex) Bit 5, Go Command (go) Bit 6

    The R/W bit specifies the direction of data transfer. Table 10-3 R/W Bit Definition Action Write the data associated with the command into the register specified by RS4–RS0. Read the data contained in the register specified by RS4–RS0. 10-6 DSP56305 User’s Manual MOTOROLA...

  • Page 383

    PAB Register for Fetch (OPABFR) 10000 PAB Register for Decode (OPABDR) 10001 PAB Register for Execute (OPABEX) 10010 Trace Buffer and Increment Pointer 10011 Reserved Address 101xx Reserved Address 11xx0 Reserved Address 11x0x Reserved Address 110xx Reserved Address MOTOROLA DSP56305 User’s Manual 10-7...

  • Page 384: Once Decoder (odec), Once Status And Control Register (oscr), Trace Mode Enable (tme) Bit 0

    10.4.3.2 Interrupt Mode Enable (IME) Bit 1 The Interrupt Mode Enable (IME) control bit, when set, causes the chip to execute a vectored interrupt to the address VBA:$06 instead of entering the Debug mode. 10-8 DSP56305 User’s Manual MOTOROLA...

  • Page 385: Software Debug Occurrence (swo) Bit 2, Memory Breakpoint Occurrence (mbo) Bit 3

    OSCR. See Table 10-5 for the definition of the OS0–OS1 bits. Table 10-5 Core Status Bits Description Description DSP56300 core is executing instructions DSP56300 core is in Wait or Stop DSP56300 core is waiting for bus DSP56300 core is in Debug mode MOTOROLA DSP56305 User’s Manual 10-9...

  • Page 386: Reserved Bits 8-23, Once Memory Breakpoint Logic, Figure 10-6 Once Memory Breakpoint Logic 0

    Address Comparator 0 Breakpoint Control Memory Limit Register 0 Memory Breakpoint Address Comparator 1 Selection Memory Limit Register 1 Breakpoint Occurred Breakpoint Counter Count = 0 ISBKPT AA0706 Figure 10-6 OnCE Memory Breakpoint Logic 0 10-10 DSP56305 User’s Manual MOTOROLA...

  • Page 387: Once Memory Address Latch (omal), Once Memory Limit Register 0 (omlr0)

    OMLR1 must be loaded by the external command controller. 10.5.5 OnCE Memory Address Comparator 1 (OMAC1) The OnCE Memory Address Comparator 1 (OMAC1) compares the current memory address (stored in OMAL0) with the OMLR1 contents. MOTOROLA DSP56305 User’s Manual 10-11...

  • Page 388: Once Breakpoint Control Register (obcr), Bits 0–1, Bits 2–3

    The Breakpoint 0 Read/Write Select bits (RW00–RW01) define the memory breakpoints 0 to occur when a memory address accesses is performed for read, write or both. See Table 10-7 for the definition of the RW00–RW01 bits. 10-12 DSP56305 User’s Manual MOTOROLA...

  • Page 389: Bits 4–5, Bits 6–7

    See Table 10-9 for the definition of the RW10–RW11 bits. Table 10-9 Breakpoint 1 Read/Write Select Table RW11 RW10 Description Breakpoint disabled Breakpoint on write access Breakpoint on read access Breakpoint read or write access MOTOROLA DSP56305 User’s Manual 10-13...

  • Page 390: Bits 8–9, Bits10–11, Once Memory Breakpoint Counter (ombc)

    OBCR, the breakpoint counter must be written afterwards. This ensures that the OnCE breakpoint logic is reset and that no previous events can affect the new breakpoint event selected. The breakpoint counter is cleared by hardware reset. 10-14 DSP56305 User’s Manual MOTOROLA...

  • Page 391: Reserved Bits 12-15, Once Trace Logic, Figure 10-8 Once Trace Logic Block Diagram

    TME bit is set in the OSCR, and the DSP56300 core exits the Debug mode by executing the appropriate command issued by the external command controller. MOTOROLA DSP56305 User’s Manual 10-15...

  • Page 392: Methods Of Entering The Debug Mode, External Debug Request During Reset Assertion

    Debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending the first command. This process is the same for any newly fetched instruction, including 10-16 DSP56305 User’s Manual MOTOROLA...

  • Page 393: Executing The Jtag Debug_request Instruction, External Debug Request During Stop Mode

    Debug mode. After receiving the acknowledge, the external command controller must negate DE before sending the first command. Note: In this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch. MOTOROLA DSP56305 User’s Manual 10-17...

  • Page 394: Software Request During Normal Activity, Enabling Trace Mode, Enabling Memory Breakpoints, Pipeline Information And Ogdbr

    Debug mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the block diagram of the Pipeline Information Registers, with the exception of the PAB registers, which are shown in Figure 10-10 on page 10-22. 10-18 DSP56305 User’s Manual MOTOROLA...

  • Page 395: Once Pdb Register (opdbr), Once Pil Register (opilr)

    Normal mode. Since there is no direct write access to the Instruction Latch, the task of restoring is accomplished by writing to OPDBR with no-GO and no-EX. In this case the data written on PDB is transferred into the Instruction Latch. MOTOROLA DSP56305 User’s Manual 10-19...

  • Page 396: Once Gdb Register (ogdbr), Trace Buffer, Once Pab Register For Fetch (opabfr)

    PDB. This is the instruction whose fetch was completed before the chip has entered the Debug mode. The OPABDR can only be read through the JTAG port. This register is not affected by the operations performed during the Debug mode. 10-20 DSP56305 User’s Manual MOTOROLA...

  • Page 397: Once Pab Register For Execute (opabex), Trace Buffer

    ‘invalid bit’ (the 25th bit). If a conditional change of flow instruction has a ‘condition false’, the invalid bit is set, thus marking this instruction as not taken. Therefore, it is imperative to read seventeen bits of MOTOROLA DSP56305 User’s Manual 10-21...

  • Page 398: Figure 10-10 Once Trace Buffer

    Decode Address (OPABDR) Execute Address (OPABEX) Trace Buffer Register 0 Circular Trace Buffer Register 1 Buffer Pointer Trace Buffer Register 2 Trace Buffer Register 11 Trace Buffer Shift Register AA0710 Figure 10-10 OnCE Trace Buffer 10-22 DSP56305 User’s Manual MOTOROLA...

  • Page 399: Once Commands And Serial Protocol, Target Site Debug System Requirements

    The external command controller circuit acts as a JTAG port driver and host computer command interpreter. The controller issues commands based on the host computer inputs from a user interface program that communicates with the user. MOTOROLA DSP56305 User’s Manual 10-23...

  • Page 400: Examples Of Using The Once, Whether The Chip Has Entered The Debug Mode

    1. Select shift-IR. Passing through capture-IR loads the core status bits into the instruction shift register. 2. Shift in ENABLE_ONCE. While shifting-in the new instruction the captured status information is shifted-out. Pass through update-IR. 3. Return to Run-Test/Idle. 10-24 DSP56305 User’s Manual MOTOROLA...

  • Page 401: Saving Pipeline Information, Reading The Trace Buffer

    2. Select shift-DR. Shift out the 16-bit OPABFR register. Pass through update-DR. 3. Select shift-DR. Shift in the “Read PABDR”. Pass through update-DR. 4. Select shift-DR. Shift out the 16-bit OPABDR register. Pass through update-DR. 5. Select shift-DR. Shift in the “Read PABEX”. Pass through update-DR. MOTOROLA DSP56305 User’s Manual 10-25...

  • Page 402: Displaying A Specified Register

    4. Select shift-DR and shift in “READ GDB REGISTER”. Pass through update-DR (this selects OGDBR as the data register for read). 5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. Wait for next command. 10-26 DSP56305 User’s Manual MOTOROLA...

  • Page 403: Displaying X Memory Area Starting At Address $xxxx

    13. Wait for DSP to reenter Debug mode (wait for DE or poll core status). 14. Select shift-DR and shift in “READ GDB REGISTER”. Pass through update-DR (this selects OGDBR as the data register for read). MOTOROLA DSP56305 User’s Manual 10-27...

  • Page 404: Going From Debug To Normal Mode In A Current Program

    Therefore, the user must force a “change of flow” to the starting address of the new program ($xxxx). The sequence of actions is: 1. Select shift-DR. Shift in the “Write PDB with no-GO no-EX”. Pass through update-DR. 10-28 DSP56305 User’s Manual MOTOROLA...

  • Page 405: Examples Of Jtag And Once Interaction

    After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and after the core status was polled to verify that the chip is in Debug mode, the pipeline saving procedure must take place. The TMS sequencing for this procedure is depicted in Table 10-12. MOTOROLA DSP56305 User’s Manual 10-29...

  • Page 406

    11, indicating that the chip has entered the Debug mode. If the chip has not yet entered the Debug mode, the external command controller goes to “step b”, “step c” etc. until the Debug mode is acknowledged. 10-30 DSP56305 User’s Manual MOTOROLA...

  • Page 407

    Table 10-14 TMS Sequencing for Reading Pipeline Registers Step JTAG Port OnCE Module Note Run-Test/Idle Idle Select-DR-Scan Idle Capture-DR Idle Shift-DR Idle The eight bits of the OnCE command “Read PIL” ..............(10001011) are shifted in. Shift-DR Idle Exit1-DR Idle MOTOROLA DSP56305 User’s Manual 10-31...

  • Page 408

    Idle Update-DR Execute “Read PDB” PDB value is loaded in shifter Select-DR-Scan Idle Capture-DR Idle Shift-DR Idle The 24 bits of the PDB are shifted out (24 steps)..............Shift-DR Idle Exit1-DR Idle Update-DR Idle 10-32 DSP56305 User’s Manual MOTOROLA...

  • Page 409

    ..........command controller to analyze the information. Run-Test/Idle Idle During “step v” the external command controller stores the pipeline information and afterwards it can proceed with the debug activities as requested by the user. MOTOROLA DSP56305 User’s Manual 10-33...

  • Page 410

    On-Chip Emulation Module Examples of JTAG and OnCE interaction 10-34 DSP56305 User’s Manual MOTOROLA...

  • Page 411: Section 11 Jtag Port, Jtag Port

    SECTION 11 JTAG PORT MOTOROLA DSP56305 User’s Manual 11-1...

  • Page 412: Table Of Contents

    TAP Controller ........11-6 11.4 DSP56300 Restrictions ......11-12 11-2 DSP56305 User’s Manual MOTOROLA...

  • Page 413

    DSP56300 core implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. Figure 11-1 shows a block diagram of the TAP port. MOTOROLA DSP56305 User’s Manual 11-3...

  • Page 414: Figure 11-1 Tap Block Diagram

    JTAG Port Introduction Boundary Scan Register Bypass ID Register OnCE Logic Decoder 4-Bit Instruction Register Ctrl TRST AA0113 Figure 11-1 TAP Block Diagram 11-4 DSP56305 User’s Manual MOTOROLA...

  • Page 415: Jtag Signals, Test Clock (tck), Test Mode Select (tms), Test Data Input (tdi)

    As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four signals to support TDI, TDO, TCK, and TMS signals. The DSP56300 family also provides the optional TRST signal. On the DSP56305, the Debug Event (DE) signal is provided for use by the OnCE module; it is described in .

  • Page 416: Tap Controller, Figure 11-2 Tap Controller State Machine

    TMS signal sampled on the rising edge of TCK signal. For a description of the TAP controller states, please refer to the IEEE 1149.1 document. Test-Logic-Reset Select-IR-Scan Run-Test/Idle Select-DR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-IR Pause-DR Exit2-DR Exit2-IR Update-DR Update-IR AA0114 Figure 11-2 TAP Controller State Machine 11-6 DSP56305 User’s Manual MOTOROLA...

  • Page 417: Boundary Scan Register, Instruction Register, Figure 11-3 Jtag Instruction Register

    All DSP56305 bidirectional signals have a single register bit in the BSR for signal data, and are controlled by an associated control bit in the BSR. The DSP56305 BSR bit definitions are described in Table 11-2.

  • Page 418

    01 in the Least Significant Bits as required by the standard. The two Most Significant Bits are loaded with the values of the core status bits OS1 and OS0 from the OnCE controller. See , for a description of the Section 10, On-Chip Emulation Module status bits. 11-8 DSP56305 User’s Manual MOTOROLA...

  • Page 419: Extest (b[3:0] = 0000), Sample/preload (b[3:0] = 0001), Idcode (b[3:0] = 0010)

    The IDCODE instruction selects the ID register. This instruction is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the TAP. Figure 11-4 shows the ID register configuration. MOTOROLA DSP56305 User’s Manual 11-9...

  • Page 420: Clamp (b[3:0] = 0011), Figure 11-4 Jtag Id Register

    21:12). The sequence number is divided into two parts: Core Number (bits 21:17) and Chip Derivative Number (bits 16:12). Motorola Semiconductor IsraeL (MSIL) Design Center Number is 000110 and DSP56300 core number is 00001. For the DSP56305, the chip derivative number is 00011.

  • Page 421: Hi-z (b[3:0] = 0100), Enable_once(b[3:0] = 0110), Debug_request(b[3:0] = 0111)

    (acknowledged by the combination 11 on OS1–OS0). After acknowledgment of the Debug mode is received, the external JTAG controller must issue the ENABLE_ONCE instruction to allow the user to perform system debug functions. MOTOROLA DSP56305 User’s Manual 11-11...

  • Page 422: Bypass (b[3:0] = 1111), Dsp56300 Restrictions, Figure 11-5 Bypass Register

    After power-up is concluded, TMS must be sampled as a logic 1 for five consecutive TCK rising edges. If TMS either remains unconnected or is connected to , then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the state of TCK. 11-12 DSP56305 User’s Manual MOTOROLA...

  • Page 423: Dsp56305 Boundary Scan Register

    V achieve minimal power consumption. Since during Stop mode all DSP56305 core clocks are disabled, the JTAG interface provides the means of polling the device status (sampled in the Capture-IR state).

  • Page 424

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type Input/Output Data Input/Output Data Input/Output Data D[23:13] — Control Input/Output Data Input/Output Data Input/Output Data...

  • Page 425

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type Tri-State Data Tri-State Data Tri-State Data Tri-State Data Tri-State Data Tri-State Data Tri-State Data Tri-State...

  • Page 426

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type Input/Output Data Output Data Input Data BCLK Tri-State Data BCLK Tri-State Data CLKOUT Output Data RD, WR, —...

  • Page 427

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type HAD4 — Control HAD4 Input/Output Data HAD5 — Control HAD5 Input/Output Data HAD6 — Control...

  • Page 428

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type HREQ/TR Input/Output Data HACK/R — Control HACK/R Input/Output Data HRW/RD — Control HRW/RD Input/Output Data HDS/WR —...

  • Page 429

    JTAG Port DSP56305 Boundary Scan Register Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued) Bit # Pin Name Pin Type BSR Cell Type STD0 Input/Output Data SRD0 — Control SRD0 Input/Output Data PINIT Input Data — Control Input/Output...

  • Page 430

    JTAG Port DSP56305 Boundary Scan Register 11-20 DSP56305 User’s Manual MOTOROLA...

  • Page 431: Section 12 Filter Co-processor

    Filter Co-Processor SECTION 12 FILTER CO-PROCESSOR MOTOROLA DSP56305 User’s Manual 12-1...

  • Page 432

    Operation Modes ........12-14 12.6 Performance Analysis ......12-40 12-2 DSP56305 User’s Manual MOTOROLA...

  • Page 433: Fcop Support For Gsm, Introduction

    • Special optimized mode (Mode 2) for performing matched filtering required for channel equalization using the Ungerboeck scheme • Internal data and coefficient memory banks supports GSM normal burst, as well as GSM access burst. MOTOROLA DSP56305 User’s Manual 12-3...

  • Page 434: Features, Block Description

    Data Input Buffer, Coefficients Input Buffer, Output Buffer, and Filter Counter (FCNT)—, FCOP Data Memory Bank (FDM), FCOP Coefficients Memory Bank (FCM), FCOP MAC machine (FMAC), Address Generator, and Control Logic. The block diagram is presented in Figure 12-1. 12-4 DSP56305 User’s Manual MOTOROLA...

  • Page 435: Peripheral Module Bus (pmb) Interface, Figure 12-1 Filter Co-processor Block Diagram

    The block generates the interrupt and DMA trigger signals, whenever data transfer is required. The control and status registers in the PMB are described in detail in the programming model (see Section 12.4). The interface registers are accessible to the DSP56300 core through the PMB. MOTOROLA DSP56305 User’s Manual 12-5...

  • Page 436: Fcop Memory Banks, Multiplier And Accumulator (fmac), Programming Model

    16-bit result from FMAC is stored in the FDOR to be read by the DSP56300 core. 12.4 PROGRAMMING MODEL The programming model discusses the FCOP registers available to the programmer, and interrupts and DMA access. 12-6 DSP56305 User’s Manual MOTOROLA...

  • Page 437: Fcop Registers

    Data source • FCOP Data Output Register (FDOR) Data destination • FCOP Data Input Register (FDIR) FCOP Coefficients Input Register (FCIR) • Non-data • FCOP Filter Count Register (FCNT) • FCOP Control Status Register (FCSR) MOTOROLA DSP56305 User’s Manual 12-7...

  • Page 438: Fcop Data Input Register (fdir), Fcop Data Output Register (fdor)

    DMA requests to trigger the DSP56300 core for data transfers. FDOR can be read by the DSP56300 core and DMA. FDOR is also referred to as the FCOP Data Output Buffer. 12-8 DSP56305 User’s Manual MOTOROLA...

  • Page 439: Fcop Coefficients Input Register (fcir), Fcop Filter Count Register (fcnt), Fcop Control/status Register (fcsr)

    DSP56300 core to control the main operation modes and to monitor the status of the module. The FCSR bits are described in the following paragraphs. All FCSR bits are cleared after hardware and software reset. MOTOROLA DSP56305 User’s Manual 12-9...

  • Page 440: Fcop Enable (fen)—fcsr Bit 0, Fcop Operation Mode (fom[1:0])—fcsr Bits 4–5

    FCOP operation in the various modes, refer to Figure 12.5. Table 12-4 FCOP Operation Modes FOM1 FOM0 Mode Mode Function Real FIR Filter Full Complex FIR Filter Complex FIR filter with alternate Pure Real/Imaginary outputs Optimized Complex Correlation 12-10 DSP56305 User’s Manual MOTOROLA...

  • Page 441: Fcop Decimation (fdcm)—fcsr Bit 8

    Input Buffer Empty (FDIBE is set). FDIR should be written either by the interrupt routine or the DMA transfer, but not both, so it is highly recommended to enable either the interrupt or DMA, but not both. MOTOROLA DSP56305 User’s Manual 12-11...

  • Page 442: Fcop Data Saturation (fsat)—fcsr Bit 12

    FCOP individual reset. When overflow occurs, the result will be saturated to the most positive number $7FFF. When underflow occurs, the result will be saturated to the most negative number $8000. MOTOROLA DSP56305 User’s Manual 12-12...

  • Page 443: Fcop Reserved Unused Bits—fcsr Bits 1, 3, 9, 13

    These bits are reserved and unused. They read as zeroes and should be written with zero for future compatibility. 12.4.6.10 FCOP Reserved Used Bits—FCSR Bits 2, 6, 7 These bits are reserved for internal testing and debugging. They must be written with zeroes for proper operation. MOTOROLA DSP56305 User’s Manual 12-13...

  • Page 444: Interrupts And Dma, Operation Modes

    The following sections describe the operation of FCOP in each mode, either with no decimation or with decimation by two. The description includes: equation of the implemented filter, initialization and processing steps, data and coefficients input scheme, output data scheme. MOTOROLA DSP56305 User’s Manual 12-14...

  • Page 445: Terminology Used In This Section, Input Dma Activation

    A good practice is to program the input data DMA channel for single word transfer or line of 2, 3, or 4 word transfer (since the input buffer FIFO depth is 4), triggered by the FDIBE bit in FCSR. MOTOROLA DSP56305 User’s Manual 12-15...

  • Page 446: Output Dma Activation, Decimation By 2

    FDM and then performs the FIR calculation on the second input data items only. This is equivalent to performing the full FIR filter but reading only every second FIR result, thus saving half the calculations. MOTOROLA DSP56305 User’s Manual 12-16...

  • Page 447: Fcop Mode 0: Real Fir Filter, Mode 0 (real Fir Filter), No Decimation

    DMA to transfer up to four new data words to FDM via FDIR • Compute F(n) and store result in FDOR • FCOP triggers core or DMA for output data transfer • Get new data word • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-17...

  • Page 448: Without Decimation

    D(4) H(4) Bank Bank Output Data D(5) H(3) (FDM) (FCM) Stream — — F(0) — F(1) F(2) F(3) F(4) F(5) — — AA1122 Figure 12-3 Input and Output Stream for Real FIR Filter without Decimation MOTOROLA DSP56305 User’s Manual 12-18...

  • Page 449: Mode 0 (real Fir Filter), Decimation By 2

    • Compute F(n) and store result in FDOR • FCOP triggers core or DMA for output data transfer • Get new data word • FCOP increments data memory pointer • Get new data word • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-19...

  • Page 450: With Decimation By 2

    Bank Bank Output Data D(5) H(3) (FDM) (FCM) Stream — — F(0) — F(2) F(4) F(6) F(8) F(10) — — AA1123 Figure 12-4 Input and Output Stream for Real FIR Filter with Decimation by 2 MOTOROLA DSP56305 User’s Manual 12-20...

  • Page 451: Real Outputs Only), Decimation By 2

    • Compute F(n) and store result in FDOR • FCOP triggers core or DMA for output data transfer • Get new data word • FCOP increments data memory pointer • Get new data word • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-21...

  • Page 452

    DI(2) –HI(6) (FDM) (FCM) Stream — — FR(0) — FR(1) FR(2) FR(3) FR(4) FR(5) — — AA1124 Figure 12-5 Input and Output Stream for Complex FIR Filter Generating Real Outputs Only with Decimation by 2 MOTOROLA DSP56305 User’s Manual 12-22...

  • Page 453: Fcop Mode 1: Full Complex Fir Filter, Mode 1(full Complex Fir Filter), No Decimation

    • Compute FI(n) and store result in FDOR • FCOP triggers core or DMA for output data transfer • Get new data word (DR) • FCOP increments data memory pointer • Get new data word (DI) • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-23...

  • Page 454

    HR(6) Bank Bank Output Data DI(2) HI(6) (FDM) (FCM) Stream — — FR(0) — FI(0) FR(1) FI(1) FR(2) FI(2) — — AA1125 Figure 12-6 Input and Output Stream for Full Complex FIR Filter without Decimation MOTOROLA DSP56305 User’s Manual 12-24...

  • Page 455: No Decimation

    • Compute FI(n) and store result in FDOR • FCOP triggers core or DMA for output data transfer • Get new data word (DR) • FCOP increments data memory pointer • Get new data word (DI) • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-25...

  • Page 456

    HR(2) Bank Bank Output Data DI(2) –HI(2) (FDM) (FCM) Stream — — FR(0) — FI(0) FR(1) FI(1) FR(2) FI(2) — — AA1126 Figure 12-7 Input and Output Stream for Full Complex Correlation Filter without Decimation MOTOROLA DSP56305 User’s Manual 12-26...

  • Page 457: Mode 1 (full Complex Fir Filter), Decimation By 2

    • Get new data word (DI) • FCOP increments data memory pointer • Get new data word (DR) • FCOP increments data memory pointer • Get new data word (DI) • FCOP increments data memory pointer MOTOROLA DSP56305 User’s Manual 12-27...

  • Page 458: With Decimation

    DR(2) HR(6) Bank Bank Output Data DI(2) HI(6) (FDM) (FCM) Stream — — FR(0) — FI(0) FR(2) FI(2) FR(4) FI(4) — — AA1127 Figure 12-8 Input and Output Stream for Full Complex Filter with Decimation MOTOROLA DSP56305 User’s Manual 12-28...

  • Page 459: Fcop Mode 2: Full Complex Fir Filter

    FCOP (FEN = 1) • Core initializes coefficients in FCM in reverse order by executing Initialization #filter_count writes to FCIR • Core or DMA initializes data in FDM in direct order by executing #filter_count writes to FDIR MOTOROLA DSP56305 User’s Manual 12-29...

  • Page 460

    (FDM) (FCM) Stream — — FR(0) — FI(1) FR(2) FI(3) FR(4) FI(5) — — AA1128 Figure 12-9 Input and Output Stream for Complex FIR Filter Generating Pure Real or Pure Imaginary Outputs Alternately without Decimation MOTOROLA DSP56305 User’s Manual 12-30...

  • Page 461: Mode 2 (complex Fir Filter Generating Pure Real And Pure Imaginary Outputs Alternately), Decimation By 2

    FR n – , , , 0 4 8 etc – ∑ HR i ( ) DI n i – ⋅ HI i ( ) DR n i – ⋅ FI n 2 6 10 etc MOTOROLA DSP56305 User’s Manual 12-31...

  • Page 462

    • Get new data word (DI) • FCOP increments data memory pointer • Get new data word (DR) • FCOP increments data memory pointer • Get new data word (DI) • FCOP increments data memory pointer 12-32 DSP56305 User’s Manual MOTOROLA...

  • Page 463

    Stream — — FR(0) — FI(2) FR(4) FI(6) FR(8) FI(10) — — AA1129 Figure 12-10 Input and Output Stream for Complex FIR Filter Generating Pure Real and Pure Imaginary Outputs Alternately with Decimation by 2 MOTOROLA DSP56305 User’s Manual 12-33...

  • Page 464: Fcop Mode 3: Optimized Complex Correlation Function, No Decimation

    Decimation The received training sequence is complex (one pair of I&Q samples per bit). The midamble sequence consists of alternate pure real/pure imaginary values (one pure complex value per bit). Refer to the following table: 12-34 DSP56305 User’s Manual MOTOROLA...

  • Page 465

    ( ) DR n 2i ⋅ ) DI n ⋅ HR 2i HI 2i N 2 ⁄ 1 – ∑ FI n ( ) ( ) DI n ⋅ ) DR n ⋅ HR 2i – HI 2i MOTOROLA DSP56305 User’s Manual 12-35...

  • Page 466

    Bank Bank Output Data DI(2) HI(5) (FDM) (FCM) Stream — — FR(0) — FI(0) FR(1) FI(1) FR(2) FI(2) — — AA1130 Figure 12-11 Input and Output Stream for Complex Correlation of Non-Oversampled Data without Decimation 12-36 DSP56305 User’s Manual MOTOROLA...

  • Page 467

    When n is even, the filter outputs are independent of the odd input samples, and when n is odd, the filter outputs are independent of the even input samples. As a result, even and odd outputs can be calculated separately, requiring half of the data memory bank size. MOTOROLA DSP56305 User’s Manual 12-37...

  • Page 468

    • Compute FI(n) and store result in FDOR. • FCOP triggers core or DMA for output data transfer. • Get new data word (DR). • FCOP increments data memory pointer. • Get new data word (DI). • FCOP increments data memory pointer. 12-38 DSP56305 User’s Manual MOTOROLA...

  • Page 469

    Bank Output Data DI(4) HI(10) (FDM) (FCM) Stream — — FR(0) — FI(0) FR(2) FI(2) FR(4) FI(4) — — AA1131 Figure 12-12 Input and Output Stream for Complex Correlation of 2× Oversampled Data without Decimation MOTOROLA DSP56305 User’s Manual 12-39...

  • Page 470: Performance Analysis

    9 x 2 1474 38.5 µs Normal Correlation 26 x 2 52 x 2 3078 11.6 µs Access Match Filter 36 x 2 9 x 2 91.5 µs Access Correlation 41 x 2 82 x 2 7308 12-40 DSP56305 User’s Manual MOTOROLA...

  • Page 471: Section 13 Viterbi Co-processor

    VITERBI CO-PROCESSOR SECTION 13 VITERBI CO-PROCESSOR MOTOROLA DSP56305 User’s Manual 13-1...

  • Page 472

    Performance Analysis ......13-34 13.9 Programming Examples ......13-37 13-2 DSP56305 User’s Manual MOTOROLA...

  • Page 473: Vcop Support For Gsm, Introduction, Figure 13-1 Block Diagram Of A Typical Data Communication System

    Figure 13-1 Block Diagram of a Typical Data Communication System The blocks using the VCOP (framed in bold, above) are convolutional encoding, convolutional decoding, and channel equalization. The next section gives an example of using the Viterbi algorithm for channel equalization. MOTOROLA DSP56305 User’s Manual 13-3...

  • Page 474: Mlse Equalizer, Figure 13-2 Ungerboeck Form Of Mlse Channel Equalizer

    Signal-to-Noise Ratio (SNR) values over hard-decision-only convolutional decoders. Compute Channel Impulse Response Input Compute MF Compute Hard Decision Auto- MLSE Data Coefficients correlation L-Metrics Equalized Data Matched Filter AA1312 Figure 13-2 Ungerboeck Form of MLSE Channel Equalizer 13-4 DSP56305 User’s Manual MOTOROLA...

  • Page 475

    3. Koch, Wolfgang, and Baier, Alfred 1990. “Optimum and Sub-optimum Detection of Coded Data Disturbed by Time-varying Intersymbol Interference,” in Communications: Connecting the Future, vol. 3:1679–1684. Global Telecommunications Conference and Exhibition, San Diego, Dec. 2–5, 1990. (IEEE catalog number 90CH2827–4). MOTOROLA DSP56305 User’s Manual 13-5...

  • Page 476: Block Description, Figure 13-3 Vcop Block Diagram

    2 × 17 Metric Trellis brma,b Output Buff tab_survivor surv. bit 63 × 16 bit / 1023 × 1 bit Metric Trellis Delay Addr DELAY Receive Quality Convolutional Encoder AA1313 Figure 13-3 VCOP Block Diagram 13-6 DSP56305 User’s Manual MOTOROLA...

  • Page 477: Flow Control, Peripheral Module Bus (pmb) Interface, Branch Metric

    For every ACS butterfly there are two associated VP values. When performing equalization, the calculation is based on demodulated symbol data which is the output of a Matched Filter (MF). The MF value is stored in the VDR as a 16-bit value. MOTOROLA DSP56305 User’s Manual 13-7...

  • Page 478: Add-compare-select (acs), Window Error Detection (wed), Figure 13-4 Window Error Detection Function

    WED. The block updates WED RAM with the minimal-difference decision along every path within the WED window. Previous State’s Decision WED RAM Minimal Difference Difference Update State’s Minimal Difference AA1314 Figure 13-4 Window Error Detection Function 13-8 DSP56305 User’s Manual MOTOROLA...

  • Page 479: Trellis, Data Control, Receive Quality Error, Figure 13-5 Bit Error Count Function

    The BER value is true only if the data was successfully decoded, so the decoding should be checked using CRC. Soft Symbol Viterbi Encoder Algorithm Hard Symbol Delay BER Count AA1315 Figure 13-5 Bit Error Count Function MOTOROLA DSP56305 User’s Manual 13-9...

  • Page 480: Equalization Mode, Operating Modes

    The equalizer should be supplied with the Viterbi parameters (VP) - the state transition metrics for the equalization scheme, based on the linear combination of the channel impulse response coefficients. 13-10 DSP56305 User’s Manual MOTOROLA...

  • Page 481: Initialization, Normal Operation, Flush Operation, Figure 13-6 Viterbi Co-processor In Equalization Mode

    In this stage, there are no more MF inputs and only the remaining bits in the trellis memory are left to process. The trellis path is selected according to the Flush Control mode (ending state or best metric), and the remaining bits are shifted out. MOTOROLA DSP56305 User’s Manual 13-11...

  • Page 482: Encoder Mode, Initialization, Decoder Mode, Figure 13-7 Viterbi Co-processor In Encoder Mode

    The Manhattan metric system is used. The decoder provides the Bit Error count (BER), the number of bits corrected by the decoder. The BER is available to the DSP56300 core as the contents of the (read-only) VBER. 13-12 DSP56305 User’s Manual MOTOROLA...

  • Page 483: Normal Operation, Initialization, Figure 13-8 Viterbi Co-processor In Decoder Mode

    The survivor is found by the ACS block and a decoded bit is delivered from the Trellis block to the output buffer. The decoded data is re-encoded by the BER block to be compared with the original input symbol. MOTOROLA DSP56305 User’s Manual 13-13...

  • Page 484: Flush Operation, Memory Access Mode, Flush Mode

    DECEN or EQEN and setting the FLEN bit in VCRA. In this case the VCOP will suspend the current processing and start the flush operation as described above. 13-14 DSP56305 User’s Manual MOTOROLA...

  • Page 485: Vcop Individual Reset State, Idle State

    Control bits and OPC status bit in VSTR are preserved, while the remaining status bits in VSTR are cleared. MOTOROLA DSP56305 User’s Manual 13-15...

  • Page 486

    That is. the registers are read zero padded ($00DDDD) and written with the eight MSBs ignored ($XXDDDD). When writing the control registers from a 24-bit resource, the 8 MSBs must be written with 0 for future compatibility. 13-16 DSP56305 User’s Manual MOTOROLA...

  • Page 487: Viterbi Data Register/fifo (vdr), Viterbi Data Out Register (vdor)

    In decoding, the VDOR holds the decoded bit in the same hard value format ($800000 for ‘1’ or $7FFF00 for ‘0’) and should be written with 16-bit words of packed decoded bits. In equalization, the VDOR holds a hard value. Consecutive single cycle reads of VDOR are not allowed. MOTOROLA DSP56305 User’s Manual 13-17...

  • Page 488: Viterbi Control Register A (vcra), Module Enable (me)—vcra Bit 0

    RAMs. The VBER contains the address of the memory access while VMEM contains the data. This mode is used when setting the SP and VP values for channel equalization. After setting these parameters, the MAEN bit must be cleared by the DSP56300 core. 13-18 DSP56305 User’s Manual MOTOROLA...

  • Page 489: Decoding Enable (decen)—vcra Bit 2, Encoding Enable (encen)—vcra Bit 3, Equalization Enable (eqen)—vcra Bit 4

    Trellis RAM. The path to be flushed is defined by the VTSR register. At the end of the flush operation the FLEN bit is cleared by the internal logic. MOTOROLA DSP56305 User’s Manual 13-19...

  • Page 490: Code Rate (rate[1:0])—vcra Bits 8–9, Constraint Length (cnst[1:0])—vcra Bit 12–13

    The bit settings defining constraint length and number of trellis states are given in Table 13-3. Table 13-3 Trellis States CNST[1:0] Number of trellis states Constraint length 13.5.3.9 VCRA Reserved—VCRA Bits 6–7, 10–11, 14–15 These bits are reserved and should be written with zero. 13-20 DSP56305 User’s Manual MOTOROLA...

  • Page 491: Viterbi Control Register B (vcrb), Initial State Enable (ise)—vcrb Bit 0

    When CME is set, the VCNT contents are ignored and the VCOP operates continuously upon receiving new data words. When CME is set, the flush operation does not take place as part of the decoding and equalization process, and bits ENCEN, MOTOROLA DSP56305 User’s Manual 13-21...

  • Page 492: Data Mode (hd[0])—vcrb Bits 4–5, Window Error Detection Enable (wede)—vcrb Bit 6

    Data Mode (HD[0])—VCRB Bits 4–5 The Data Mode bit (HD[0]) defines whether hard decision data bits are available for performing channel equalization. In the current revision of the DSP56305, only hard decision data bits are available. Table 13-5 Data Modes...

  • Page 493: Internal Reserved Bits—vcrb Bits 4, 7, Viterbi Status Register (vstr), Initialize Flag (init)—vstr Bit 0

    (MAEN, DECEN, ENCEN, EQEN, and FLEN) is set. When OPC and OCIE are set, an interrupt request is generated and OPC is cleared upon servicing that interrupt request. This bit is disabled when CME (VCRB Bit 3) is set. MOTOROLA DSP56305 User’s Manual 13-23...

  • Page 494: Processing Done (done)—vstr Bit 5, Data Ready (drdy)—vstr Bit 6, End Stage (estg)—vstr Bit 7

    (VDOR) is full, causing processing to stop at the end of the current stage. The DOBF is cleared by reading the VDOR register, thus enabling further processing. 13.5.5.9 Reserved Bits—VSTR Bits 2, 3, 10–15 These bits are reserved and should be written with zero. 13-24 DSP56305 User’s Manual MOTOROLA...

  • Page 495: Viterbi Data Counter (vcnt), Viterbi Tap A Register (vtpa), Tap Vector A (tapa{4:0])—vtpa Bits 4–0

    Tap Vector C (TAPC[4:0])—VTPA Bits 14–10 The Tap Vector C (TAPC[4:0]) bits contain the vector 2 taps (G ), excluding its MSB and LSB. 13.5.7.4 Reserved Bit—VTPA Bit 15 This bit is reserved and should be written with zero. MOTOROLA DSP56305 User’s Manual 13-25...

  • Page 496: Viterbi Tap Register B (vtpb), Tap Vector D (tapd{4:0])—vtpb Bits 4–0

    Tap Vector F (TAPF[4:0])—VTPB Bits 14–10 The Tap Vector F (TAPF[4:0]) bits contain the vector 5 taps (G ), excluding its MSB and LSB. 13.5.8.4 Reserved Bit—VTPB Bit 15 This bit is reserved and should be written with zero. 13-26 DSP56305 User’s Manual MOTOROLA...

  • Page 497: Viterbi Trellis Setup Register (vtsr), Initial State (is[5:0])—vtsr Bits 5–0, End State (es[5:0])—vtsr Bits 13–8

    BER value is the number of symbol-bits corrected so far by the decoding process. The register value is valid at the end of decoding. In Memory Access mode, the VBER is a read/write address register/counter for accessing memory modules of the VCOP. Bits 7–6 select the accessed RAM module MOTOROLA DSP56305 User’s Manual 13-27...

  • Page 498: Viterbi Wed Setup Register (vwes), Figure 13-15 Viterbi Wed Setup Register (vwes)

    The WED function is operational for block sizes of up to 256 decoded bits, that is, ≤ if VCNT 256. WLEN7 WLEN6 WLEN5 WLEN4 WLEN3 WLEN2 WLEN1 WLEN0 WSTR7 WSTR6 WSTR5 WSTR4 WSTR3 WSTR2 WSTR1 WSTR0 AA1324 Figure 13-15 Viterbi WED Setup Register (VWES) 13-28 DSP56305 User’s Manual MOTOROLA...

  • Page 499: Vwes Bits 7–0, Window Length (wlen[7:0])—vwes Bits 15–8, Viterbi Wed Data Register (vwed)

    VBER, see Table 13-7 on page 30. WED accuracy, (as given in the VWED register), is plus or minus one of the correct minimal difference decision along the surviving path. MOTOROLA DSP56305 User’s Manual 13-29...

  • Page 500: Chip Description, Memory Description

    VITERBI CO-PROCESSOR Chip Description 13.6 CHIP DESCRIPTION This section describes the memory, interrupts, DMA source, and soft decision formats of the VCOP of the DSP56305. 13.6.1 Memory description Table 13-7 Memory modules usage and access Operation Modes Using the Module...

  • Page 501: Interrupt And Dma Sources, I/o Register And Related Interrupts For Different Modes

    Symbol-Bit, Soft Value VDOR DOIE DRDY Hard Decoded Value Encoding DIIE DREQ Hard Input to Encoder VDOR DOIE DRDY Symbol-Bit Output Note: A sequential write of all symbol-bits to VDR-FIFO is required for each request. MOTOROLA DSP56305 User’s Manual 13-31...

  • Page 502: Soft Decision Format

    Table 13-10 Soft Decision Format 8-bit Precision 16-bit Precision Soft Value (Symbol Input to Decoder) (Equalizer Output) Strong ‘0’ 0x7F0000 0x7FFF00 Weak ‘0’ 0x010000 all other values Neutral value 0x000000 reserved Weak ‘1’ 0xFF0000 Strong ‘1’ 0x800000 0x800000 13-32 DSP56305 User’s Manual MOTOROLA...

  • Page 503: Viterbi Butterfly Implementation, Figure 13-16 Viterbi Butterfly Structure

    L-metric table in the VP RAM. For a 64-state trellis (constraint length equals 7), the VP values for each state are calculated in an analogous way making use of S parameters S to S MOTOROLA DSP56305 User’s Manual 13-33...

  • Page 504

    The VCOP processing time for other codes can be estimated using the following equations, where values are as shown in Table 13-12 : Table 13-12 Variables for Calculating Processing Time Symbol Number Meaning Trellis_States Bits_to_Process 13-34 DSP56305 User’s Manual MOTOROLA...

  • Page 505

    The equations for processing time are derived from the following: • Total processing time (T TotalProcess × Bits_to_Process TotalProcess stage flush readbuff • Time to perform one stage (T stage × --------- - Trellis_States stage MOTOROLA DSP56305 User’s Manual 13-35...

  • Page 506

    This equation has not been verified, and may be inaccurate. Note: – In decoding, the time for BER calculation time at flush is: × 576T flush • Time required for reading data out of the VCOP (T readbuff × Bits_Left_in_Buffer readbuff 13-36 DSP56305 User’s Manual MOTOROLA...

  • Page 507: Programming Examples, Channel Encode

    #5,y:M_VSTR,* ; wait till Proc_Done rep #122 ; 122 output bits from encoder (Rate=1/2) movep y:M_VDOR,y:(r5)+ jclr #4,y:M_VSTR,* ; wait till OPC stop org x:$200 ; Input to the Encoder $800000 $800000 $7F0000 MOTOROLA DSP56305 User’s Manual 13-37...

  • Page 508

    $7F0000 $800000 $7F0000 $800000 $800000 $7F0000 $7F0000 $800000 $7F0000 $7F0000 $7F0000 $800000 $800000 $7F0000 $7F0000 $800000 $800000 $7F0000 $7F0000 $800000 $800000 $7F0000 $7F0000 $800000 $800000 $7F0000 $7F0000 $800000 $800000 $800000 $800000 $7F0000 $7F0000 $800000 $7F0000 13-38 DSP56305 User’s Manual MOTOROLA...

  • Page 509

    VITERBI CO-PROCESSOR Programming Examples $800000 $800000 $7F0000 $7F0000 $800000 MOTOROLA DSP56305 User’s Manual 13-39...

  • Page 510: Channel Decode

    ; read WED value rep #61 ; read decoded bits from output buffer movep y:M_VDOR,y:(r5)+ jclr #4,y:M_VSTR,* ; wait till OPC stop org x:$0 ; Input to decoder, 61x3 symbols $800000 $800000 $800000 13-40 DSP56305 User’s Manual MOTOROLA...

  • Page 511

    $800000 $800000 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $7fff00 MOTOROLA DSP56305 User’s Manual 13-41...

  • Page 512

    $7fff00 $800000 $800000 $800000 $7fff00 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $7fff00 $800000 $7fff00 $800000 $7fff00 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $7fff00 $7fff00 $7fff00 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $800000 $7fff00 $800000 13-42 DSP56305 User’s Manual MOTOROLA...

  • Page 513

    $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $800000 $800000 $7fff00 $800000 $7fff00 $7fff00 $800000 $800000 $7fff00 $7fff00 $800000 $7fff00 $7fff00 $7fff00 $7fff00 $800000 MOTOROLA DSP56305 User’s Manual 13-43...

  • Page 514

    VITERBI CO-PROCESSOR Programming Examples $800000 $7fff00 $800000 $7fff00 $800000 $7fff00 $800000 $7fff00 $7fff00 $800000 $800000 $800000 $7fff00 $7fff00 $800000 $800000 $800000 $7fff00 $800000 $7fff00 $800000 13-44 DSP56305 User’s Manual MOTOROLA...

  • Page 515: Including Read/write Memory Access

    ; Memory access to initialize the SP memory (not necessary) ;************************************ movep #$0040,y:M_VBER ; SP memory address rep #7 movep x:(r4)+,y:M_VMEM ; Load SP ;************************************ ; Example of memory access to read the VP memory in VCOP (not necessary) ;************************************ MOTOROLA DSP56305 User’s Manual 13-45...

  • Page 516

    ; wait till OPC ;************************************ ; Process Second Half of Normal Burst ;************************************ ; Initialize input DMA channel movep #$200,x:M_DSR0 ; source address movep #M_VDR,x:M_DDR0 ; destination address movep #60,x:M_DCO0 ; 61 bits (61 transfers) 13-46 DSP56305 User’s Manual MOTOROLA...

  • Page 517

    $f33100 dc $f47f00 dc $fad600 dc $135700 dc $fc4800 dc $f30000 dc $076800 dc $0be400 dc $03db00 dc $115000 dc $062b00 dc $f2ed00 dc $052600 dc $f40f00 dc $071500 dc $0a8400 dc $ee7300 dc $0ac800 MOTOROLA DSP56305 User’s Manual 13-47...

  • Page 518

    $ffca00 dc $003500 dc $003500 dc $ffca00 dc $ffca00 dc $003500 dc $003500 org x:$200 ; Second half Input data (output of Match Filter) dc $f73200 dc $edfc00 dc $f0b200 dc $063500 dc $f57a00 13-48 DSP56305 User’s Manual MOTOROLA...

  • Page 519

    $049100 dc $05fc00 dc $150c00 dc $efcd00 dc $05f000 dc $013700 dc $f87400 dc $0c1e00 dc $f0f500 dc $f1a700 dc $f51e00 dc $f50a00 dc $f3c700 dc $0b5300 dc $f7b300 dc $0c8d00 dc $f87c00 dc $09c800 MOTOROLA DSP56305 User’s Manual 13-49...

  • Page 520

    VITERBI CO-PROCESSOR Programming Examples dc $05d900 dc $000000 dc $000000 13-50 DSP56305 User’s Manual MOTOROLA...

  • Page 521: References

    3. Koch, Wolfgang, and Baier, Alfred 1990. “Optimum and Sub-optimum Detection of Coded Data Disturbed by Time-varying Intersymbol Interference,” in Communications: Connecting the Future, vol. 3:1679–1684. Global Telecommunications Conference and Exhibition, San Diego, Dec. 2–5, 1990. (IEEE catalog number 90CH2827–4). MOTOROLA DSP56305 User’s Manual 13-51...

  • Page 522

    VITERBI CO-PROCESSOR References 13-52 DSP56305 User’s Manual MOTOROLA...

  • Page 523: Section 14 Cyclic Code Co-processor

    CYCLIC CODE CO-PROCESSOR SECTION 14 CYCLIC CODE CO-PROCESSOR MOTOROLA DSP56305 User’s Manual 14-1...

  • Page 524

    Programming Considerations ......14-23 14.7 Configuration Examples......14-27 14-2 DSP56305 User’s Manual MOTOROLA...

  • Page 525: Key Features, Introduction

    48 • Generates Cyclic Redundancy Code (CRC) syndrome using any generator polynomial of any degree up to 48 • Provides a 5 × 24-bit word input/output FIFO accessible via core or DMA MOTOROLA DSP56305 User’s Manual 14-3...

  • Page 526: Ccop Block Diagram, Cipher Mode Register Configuration, Figure 14-1 Ccop Block Diagram

    Step Run Counter Function Table Output Counter Control AA1300 Figure 14-1 CCOP Block Diagram 14.3.1 Cipher Mode Register Configuration Figure 14-2 shows how the control register contents relate to CFSR configuration in the Cipher modes. 14-4 DSP56305 User’s Manual MOTOROLA...

  • Page 527: Parity Coding Modes Register Configuration, Figure 14-2 Cfsr Configuration In The Cipher Modes

    0000 1000 0000 0000 0000 0000 AA1301 Figure 14-2 CFSR Configuration in the Cipher Modes 14.3.2 Parity Coding Modes Register Configuration Figure 14-3 shows how the control register contents relate to CFSR configuration in the Parity Coding modes. MOTOROLA DSP56305 User’s Manual 14-5...

  • Page 528: Ccop Programming Model, Figure 14-3 Cfsr Configuration In The Parity Coding Modes

    The registers are discussed in the following sections by functional block: • Input/Output – CCOP Data FIFO Register (CDFR) • Count Register – CCOP Count Register (CCNT) • Step Function – CCOP Step Function Select Register (CSFS), – CCOP Step Function Table A (CSFTA), 14-6 DSP56305 User’s Manual MOTOROLA...

  • Page 529

    CCOP Control Status Register CCSR CCOP Linear FeedBack Shift Register A CFSRA CCOP FeedBack Tap Register A CFBTA CCOP FeedForward Tap Register A CFFTA CCOP Bit Select Register A CBSRA CCOP Mask Register A CMSKA MOTOROLA DSP56305 User’s Manual 14-7...

  • Page 530: Ccop Data Fifo Register (cdfr)

    Data is clocked from the CDFR into the any or all of the CFSRs under the control of the Input Counter of the CCNT (IC[7:0], CCNT bits 0–7). They are shifted in Least Significant Bit (LSB) first. 14-8 DSP56305 User’s Manual MOTOROLA...

  • Page 531: Ccop Count Register (ccnt), Input Counter (ic[7:0])—ccnt Bits 7–0, Run Counter (rc[7:0])—ccnt Bits 15–8

    CFSRs are to be shifted for the run phase, without any new data being input (i.e. the data in the CFSRs will be modified only by the action of the feedback taps MOTOROLA DSP56305 User’s Manual 14-9...

  • Page 532: Output Counter (oc[6:0])—ccnt Bits 22–16, Continuous Mode (cm)—ccnt Bit 23, Step Function Registers

    The Step Function Select Register (CSFS) is a 24-bit read/write register used to select three bits from anywhere in the CFSRs. These bits form the address to the 8 × 4-bit Step Function Table. The register is composed of three bit-sized subregisters (lettered A, B, 14-10 DSP56305 User’s Manual MOTOROLA...

  • Page 533: Select Bit A (sba[4:0])—csfs Bits 4–0, Select Register A (sra[1:0])—csfs Bits 6–5

    SBB[4:0]) is connected to the second (middle byte) address line of the Step Function Table. The combination of SBB[4:0] and SRB[1:0] determine which bit of which CFSR is used as the second address line of the Step Function Table. MOTOROLA DSP56305 User’s Manual 14-11...

  • Page 534: Select Bit C (sbc[4:0])—csfs Bits 20–16, Select Register C (src[1:0])—csfs Bits 22–21

    4-bit words of the Step Function Table. In addition, CSFTB is used to enable the data input into the CFSRs during the input phase (using INE[3:0], CSFTB Bits 19–16), and to enable the data output data from the CFSRs during the output phase (using OUT[3:0], CSFTB Bits 23–20). 14-12 DSP56305 User’s Manual MOTOROLA...

  • Page 535: Input Enable Bits (ine[3:0])—csftb Bits 19–16, Figure 14-7 Step Function Table B Register (csftb)

    When the INEx bit is cleared, data input to CFSRz is disabled for the input phase. When the INEx bit is set, data input to CFSRz is enabled for the input phase. Table 14-3 lists the bit numbers and their corresponding registers. MOTOROLA DSP56305 User’s Manual 14-13...

  • Page 536: Output Enable Bits (oute[3:0])—csftb Bits 23–20, Ccop Control Status Register (ccsr)

    CCOP is operating, except for the interrupt enable bits, otherwise improper operation may result. The control bits OPM[1:0] and LRC (which select the CFSR configuration) should only be changed when CCOP is in the CCOP individual 14-14 DSP56305 User’s Manual MOTOROLA...

  • Page 537: Enable Bit (cen)—ccsr Bit 0, Processing Enable Bit (pren)—ccsr Bit 1

    The Operating Mode bits (OPM[1:0]) are used to determine the CFSR’s mode of operation. The operating modes supported in CCOP are shown in Table . OPM[1:0] should be changed only when CCOP is in CCOP individual reset. MOTOROLA DSP56305 User’s Manual 14-15...

  • Page 538: Left-right Connection Bit (lrc)—ccsr Bit 8, Halt On Zero Detect Bit (hozd)—ccsr Bit 9

    HOZD is set, Parity Coding processing terminates when any of the following are zero in the run phase: • the Run Counter • the bits specified by the Bit Select register CBSRA in Parity Coding Mode using one CFSR (OPM[1:0] = 10) 14-16 DSP56305 User’s Manual MOTOROLA...

  • Page 539: Force Shift Bit (fosh)—ccsr Bit 10, Data In Interrupt Enable Bit (diie)—ccsr Bit 12

    14.4.4.10 Parity Coding Done Interrupt Enable bit (PDIE)—CCSR Bit 15 The Parity Coding Done Interrupt Enable bit (PDIE), when set, enables the interrupt caused by terminating the CCOP Parity Coding mode processing (when PCDN, CCSR MOTOROLA DSP56305 User’s Manual 14-17...

  • Page 540: Input Buffer Empty Bit (inbe)—ccsr Bit 19, Input Fifo Empty Bit (infe)—ccsr Bit 20

    CCOP has completed all phases of the processing (i.e Input, Run, and Output phases) and all output data has been transferred to the FIFO. If CIDN and CDIE are set, a Cipher Done interrupt is generated. CIDN is cleared after reading (via CDFR) all the 14-18 DSP56305 User’s Manual MOTOROLA...

  • Page 541: Parity Coding Done Bit (pcdn)—ccsr Bit 23, Cyclic Code Processing Registers

    (for instance as CFSR) instead of individually (for instance as CFSRA, CFSRB, CFSRC, or CFSRD). In programming these registers, it is necessary to specify which of the register sets are being programmed (A, B, C, or D). MOTOROLA DSP56305 User’s Manual 14-19...

  • Page 542: Ccop Linear Feedback Shift Register (cfsrz), Ccop Feedback Tap Register (cfbtz)

    CFSRz drives the feedback line. In the Parity Coding modes, CMSKz should have only one bit set, specifying the CFSR bit from which the feedback line is driven (i.e. the degree of the generator polynomial). 14-20 DSP56305 User’s Manual MOTOROLA...

  • Page 543: Cipher Modes, Operating Modes, Normal Cipher Mode, Step-by-step Cipher Mode

    CPU-time overhead. 14.5.1.2 Step-by-step Cipher Mode When OPM[1:0] equals 01, the CCOP operates in the Step-by-step Cipher mode. In this mode the Cipher processing session halts after each step. This mode of operation enables MOTOROLA DSP56305 User’s Manual 14-21...

  • Page 544: Parity Coding Modes, Parity Coding Mode Using One Cfsr, Using Two Concatenated Cfsrs

    CFSR. CFSRB and CFSRA are positioned on the left and right sides respectively, while the LSB of CFSRB drives the MSB of CFSRA. In this mode, cyclic parity codes using generator polynomials of up to 48 14-22 DSP56305 User’s Manual MOTOROLA...

  • Page 545: Programming Considerations, Input Phase, Run Phase

    CCOP operates in Parity Mode (OPM1 = 1) and HOZD is set. In this condition the Zero Detect function is enabled on selected bits, and when zero is detected the run phase is terminated and the Run Counter is frozen. It is therefore possible for a run phase to be MOTOROLA DSP56305 User’s Manual 14-23...

  • Page 546: Output Phase, Cipher Mode Processing

    PREN and returns to the Idle state after executing one shift. Every shift must then be explicitly activated (by re-setting PREN). Step-by-step mode thus allows the programmer more intervention during Cipher processing than Normal mode. 14-24 DSP56305 User’s Manual MOTOROLA...

  • Page 547: Cipher Mode Initialization, Cipher Mode Output

    After Cipher processing is completed (i.e., CIDN is set), the DSP56300 core should read the output data sequence from the Data FIFO Register (CDFR). CIDN is cleared after all expected data words were read from CDFR. MOTOROLA DSP56305 User’s Manual 14-25...

  • Page 548: Parity Coding Processing

    Table summarizes the operations being conducted at the input and run phases in every (enabled) CFSR during a Parity Coding processing session. Table 14-8 Operations During Parity Coding Processing Input Phase Run Phase Input Data Enabled if INEx in CSFTB set Disabled Shifts Enabled Enabled 14-26 DSP56305 User’s Manual MOTOROLA...

  • Page 549: Parity Coding Mode Initialization, Parity Coding Mode Output, Configuration Examples

    G x ( ) ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ . This circuit is commonly used – for implementing shortened cyclic codes, the kind of code to which Fire codes for burst error correction belong. MOTOROLA DSP56305 User’s Manual 14-27...

  • Page 550

    22 of CFBTB and CFFTB, respectively, and so on. The twenty- fourth coefficients, g , are input into bit 0 (the least significant bit) of CFBTB and CFFTB, respectively. The twenty-fifth coefficients, g and m , are input into bit 23 (the most significant bit) of 14-28 DSP56305 User’s Manual MOTOROLA...

  • Page 551: Gsm Fire Encode

    0100 0000 0000 0000 0000 0000 Bit Select 0000 0000 0000 0000 0000 0000 Feedfwd Tap 0000 0000 0000 0000 0000 0000 Mask Tap 0000 0000 0000 0001 0000 0000 AA1309 Figure 14-10 GSM Fire Encode MOTOROLA DSP56305 User’s Manual 14-29...

  • Page 552: Gsm Fire Decode

    If the number of shifts exceeds 224 without D1 – D28 = 0 detection, data is uncorrectable. This is determined by process termination (PCDN set) while Run Counter equals zero (224 shifts done). The CFSR configuration for GSM Fire decode is shown in Figure 14-11. 14-30 DSP56305 User’s Manual MOTOROLA...

  • Page 553

    0100 0000 0000 0000 0000 0000 Bit Select 1111 0000 0000 0000 0000 0000 Feedfwd Tap 0010 1000 1000 0010 0000 0000 Mask Tap 0000 0000 0000 0001 0000 0000 AA1310 Figure 14-11 GSM Fire Decode MOTOROLA DSP56305 User’s Manual 14-31...

  • Page 554

    CYCLIC CODE CO-PROCESSOR Configuration Examples 14-32 DSP56305 User’s Manual MOTOROLA...

  • Page 555: Appendix A Bootstrap Code

    APPENDIX A BOOTSTRAP CODE MOTOROLA DSP56305 User’s Manual...

  • Page 556: A.1 Bootstrap Code For The Dsp56305

    Bootstrap Code BOOTSTRAP CODE FOR THE DSP56305 This is a listing of the default bootstrap code for the DSP56305, which is normally contained in the Bootstrap ROM. The user may modify or replace this with customized code. Contact your Motorola representative for more information.

  • Page 557

    ; the status register (HSTR) and confirm that its value is $3. ; Suggested 56301-to-56301 connection: slave master 56301/HI32 56301/PortA HA[10:3] <- A[10:3] ; selects HI32 (base address 00000000) HA[2:0] <- A[2:0] ; selects HTXR registers MOTOROLA DSP56305 User’s Manual...

  • Page 558

    HCTR HTF1-HTF0 bits and then ; correspondingly drive the 24-bit data mapped into 32-bit PCI bus word. ; Note that for the synchronization purposes, the DSP to PCI clock ratio ; should be more then 5/3. DSP56305 User’s Manual MOTOROLA...

  • Page 559

    ; 24-bit wide 56301 opcodes in the following format: | H0 | | L0 | | H1 | | L1 | ; The Host Processor must program the Host Interface to operate in the ; zero fill mode (HTF1-HTF0 = 01 in HCTR). MOTOROLA DSP56305 User’s Manual...

  • Page 560

    Host Interface, it is recommended that ; HOST Processor’s boot program will verify that the Host Interface is ; ready, by reading the status register (HSTR) and confirm that TRDY=1 ; or HTRQ=1. DSP56305 User’s Manual MOTOROLA...

  • Page 561

    ; MD:MC:MB:MA=110x, load from PCI/ISA HOST jclr #0,omr,UB2HOSTLD ; MD:MC:MB:MA=1110, load double-strob UB Host ; MD:MC:MB:MA=1111, load single-strob UB Host ;======================================================================== ; This is the routine that loads from the Host Interface in UB (UNIVERSAL) mode, MOTOROLA DSP56305 User’s Manual...

  • Page 562

    ; MD:MC:MB:MA=1101 - Host ISA ; Using self configuration mode, the base address in CBMA is written with ; $2f which corresponds to an ISA HTXR address of $2fe (Serial Port 2 Modem ; Status read only register). ISAHOSTLD DSP56305 User’s Manual MOTOROLA...

  • Page 563

    ; (also as replacment to NOP after sw reset!) movep #$3a0010,x:M_DCTR ; HM=$3 (UB) ; HIRD=1 (HIRQ_ pin - drive high enabled) ; HIRH=0 (HIRQ_ pin - handshake disabled) ; HRSP=1 (HRST pin - active low) ; HDRP=0 (HDRQ pin - active high) MOTOROLA DSP56305 User’s Manual...

  • Page 564

    ; This is the routine that loads from the Host Interface in PCI mode. ; MD:MC:MB:MA=1100 - Host PCI PCIHOSTLD bset #20,X:M_DCTR ; Configure HI32 as PCI UB3_CONT jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) A-10 DSP56305 User’s Manual MOTOROLA...

  • Page 565

    ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address jclr #2,X:M_SSR,* ; Wait for RDRF to go high movep X:M_SRXL,A2 ; Put 8 bits in A2 MOTOROLA DSP56305 User’s Manual A-11...

  • Page 566

    ; and go get another 24-bit word. bra <FINISH ; Boot from EPROM done ;======================================================================== TERMINATE enddo ; End the loop before exit. FINISH ; This is the exit handler that returns execution to normal A-12 DSP56305 User’s Manual MOTOROLA...

  • Page 567

    ; expanded mode and jumps to the RESET vector. andi #$0,ccr ; Clear CCR as if RESET to 0. jmp (r1) ; Then go to starting Prog addr. ; End of bootstrap code. Number of program words: 191. dup (START+192-*) endm MOTOROLA DSP56305 User’s Manual A-13...

  • Page 568

    Bootstrap Code A-14 DSP56305 User’s Manual MOTOROLA...

  • Page 569: Appendix B Equates

    Equates APPENDIX B EQUATES MOTOROLA DSP56305 User’s Manual...

  • Page 570

    B.2 Interrupt Equates........B-18 DSP56305 User’s Manual...

  • Page 571: B.1 Internal I/o Equates

    Equates INTERNAL I/O EQUATES ;*********************************************************************** EQUATES for DSP56305 I/O registers and ports ;*********************************************************************** page 132,55,0,0,0 ioequ ident ;---------------------------------------------------------------------- EQUATES for I/O Port Programming ;----------------------------------------------------------------------- Register Addresses M_DATH $FFFFCF ; Host port GPIO data Register M_DIRH $FFFFCE ; Host port GPIO direction Register...

  • Page 572

    ; DSP PCI Transaction Address (High) M_BL $3f0000 ; PCI Data Burst Length M_FC $c00000 ; Data Transfer Format Control Host PCI Address Register Bit Flags M_ARL $00ffff ; DSP PCI Transaction Address (Low) $0f0000 ; PCI Bus Command DSP56305 User’s Manual MOTOROLA...

  • Page 573

    $FFFF9A ; SCI Receive Data Register (high) M_SRXM $FFFF99 ; SCI Receive Data Register (middle) M_SRXL $FFFF98 ; SCI Receive Data Register (low) M_STXA $FFFF94 ; SCI Transmit Address Register M_SCR $FFFF9C ; SCI Control Register MOTOROLA DSP56305 User’s Manual...

  • Page 574

    ; Clock Divider Mask (CD0-CD11) M_COD ; Clock Out Divider M_SCP ; Clock Prescaler M_RCM ; Receive Clock Mode Source Bit M_TCM ; Transmit Clock Source Bit ;----------------------------------------------------------------------- EQUATES for Synchronous Serial Interface (SSI) ;----------------------------------------------------------------------- Register Addresses Of SSI0 DSP56305 User’s Manual MOTOROLA...

  • Page 575

    ; Serial Control 2 Direction M_SCKD ; Clock Source Direction M_SHFD ; Shift Direction M_FSL $180 ; Frame Sync Length Mask (FSL0-FSL1) M_FSL0 ; Frame Sync Length 0 M_FSL1 ; Frame Sync Length 1 M_FSR ; Frame Sync Relative Timing MOTOROLA DSP56305 User’s Manual...

  • Page 576

    SSI Receive Slot Mask Register A M_SSRSA $FFFF ; SSI Rcv Slot Bits Mask A (RS0-RS15) SSI Receive Slot Mask Register B M_SSRSB $FFFF ; SSI Rcv Slot Bits Mask B (RS16-RS31) ;---------------------------------------------------------------------- EQUATES for Exception Processing ;---------------------------------------------------------------------- DSP56305 User’s Manual MOTOROLA...

  • Page 577

    ; DMA5 Interrupt Priority Level (high) Interrupt Priority Register Peripheral (IPRP) M_HPL ; Host Interrupt Priority Level Mask M_HPL0 ; Host Interrupt Priority Level (low) M_HPL1 ; Host Interrupt Priority Level (high) M_S0L ; SSI0 Interrupt Priority Level Mask MOTOROLA DSP56305 User’s Manual...

  • Page 578

    ; TIMER2 Control/Status Register M_TLR2 $FFFF86 ; TIMER2 Load Reg M_TCPR2 $FFFF85 ; TIMER2 Compare Register M_TCR2 $FFFF84 ; TIMER2 Count Register M_TPLR $FFFF83 ; TIMER Prescaler Load Register M_TPCR $FFFF82 ; TIMER Prescalar Count Register B-10 DSP56305 User’s Manual MOTOROLA...

  • Page 579

    $FFFFF0 ; DMA Offset Register 3 Register Addresses Of DMA0 M_DSR0 $FFFFEF ; DMA0 Source Address Register M_DDR0 $FFFFEE ; DMA0 Destination Address Register M_DCO0 $FFFFED ; DMA0 Counter M_DCR0 $FFFFEC ; DMA0 Control Register MOTOROLA DSP56305 User’s Manual B-11...

  • Page 580

    ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 ; DMA Address Mode 0 M_DAM1 ; DMA Address Mode 1 M_DAM2 ; DMA Address Mode 2 M_DAM3 ; DMA Address Mode 3 M_DAM4 ; DMA Address Mode 4 B-12 DSP56305 User’s Manual MOTOROLA...

  • Page 581

    ; Mask register A M_CFSRB $FFFF90 ; Feedback shift register B M_CFTBB $FFFF91 ; Feedback tap register B M_CFFTB $FFFF92 ; Feedforward tap register B M_CBSRB $FFFF93 ; Bit select register B M_CMSKB $FFFF94 ; Mask register B MOTOROLA DSP56305 User’s Manual B-13...

  • Page 582

    ; Filter data out register M_FCIR $FFFFB2 ; Filter coefficient input register M_FCNT $FFFFB3 ; Filter counter register M_FCSR $FFFFB4 ; Filter control status register ;----------------------------------------------------------------------- EQUATES for Phase Locked Loop (PLL) ;---------------------------------------------------------------------- Register Addresses Of PLL B-14 DSP56305 User’s Manual MOTOROLA...

  • Page 583

    ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE ; Page Logic Enable M_BME ; Mastership Enable M_BRE ; Refresh Enable M_BSTR ; Software Triggered Refresh MOTOROLA DSP56305 User’s Manual B-15...

  • Page 584

    ; mask for CORE-DMA priority bits in OMR M_MA ; Operating Mode A M_MB ; Operating Mode B M_MC ; Operating Mode C M_MD ; Operating Mode D M_EBD ; External Bus Disable bit in OMR M_SD ; Stop Delay B-16 DSP56305 User’s Manual MOTOROLA...

  • Page 585

    ; Stack Extension space select bit in OMR. M_EUN ; Extensed stack UNderflow flag in OMR. M_EOV ; Extended stack OVerflow flag in OMR. M_WRP ; Extended WRaP flag in OMR. M_SEN ; Stack Extension Enable bit in OMR. MOTOROLA DSP56305 User’s Manual B-17...

  • Page 586: B.2 Interrupt Equates

    Equates INTERRUPT EQUATES ;*********************************************************************** EQUATES for DSP56305 interrupts ;*********************************************************************** page 132,55,0,0,0 intequ ident @DEF(I_VEC) ;leave user definition as is. else I_VEC endif ;----------------------------------------------------------------------- Non-Maskable interrupts ;----------------------------------------------------------------------- I_RESET I_VEC+$00 ; Hardware RESET I_STACK I_VEC+$02 ; Stack Error I_ILL I_VEC+$04 ; Illegal Instruction...

  • Page 587

    ; Host PCI Master Transmit I_HST I_VEC+$6E ; Host Slave Transmit I_HPMA I_VEC+$70 ; Host PCI Master Address I_HCNMI I_VEC+$72 ; Host Command/Host NMI (Default) ;----------------------------------------------------------------------- ; FKOP Filter Interrupts ;----------------------------------------------------------------------- I_KDIIE I_VEC+$78 ; Filter input buffer empty MOTOROLA DSP56305 User’s Manual B-19...

  • Page 588

    ; encryption output FIFO not empty I_CCIDN I_VEC+$94 ; encryption processing done I_CPCDN I_VEC+$96 ; encryption parity code processing done ;----------------------------------------------------------------------- ; INTERRUPT ENDING ADDRESS ;----------------------------------------------------------------------- I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space B-20 DSP56305 User’s Manual MOTOROLA...

  • Page 589: Appendix C Jtag Bsdl

    APPENDIX C JTAG BSDL MOTOROLA DSP56305 User’s Manual...

  • Page 590

    JTAG BSDL DSP56305 User’s Manual MOTOROLA...

  • Page 591: C.1 Jtag Bsdl File

    S S D T J T A G S O F T W A R E -- BSDL File Generated: Sun Jun 23 14:42:45 1996 -- Revision History: entity DSP56305 is generic (PHYSICAL_PIN_MAP : string := "PBGA252"); port ( DE_: inout bit;...

  • Page 592

    PGND1: linkage bit; PGND: linkage bit; BCLK_: bit); use STD_1149_1_1994.all; attribute PIN_MAP of DSP56305 : entity is PHYSICAL_PIN_MAP; constant PBGA252 : PIN_MAP_STRING := "AA: (1, 2, 20, 21), " & "NVCC: (18, 3), " & DSP56305 User’s Manual MOTOROLA...

  • Page 593

    (163, 150, 128, 117), " & "HIDSEL: 129, " & "HFRAME_: 130, " & "HIRDY_: 133, " & "HTRDY_: 134, " & "XVCC: 137, " & "HDEVSEL_: 138, " & "HSTOP_: 139, " & "HLOCK_: 140, " & MOTOROLA DSP56305 User’s Manual...

  • Page 594

    TMS : signal is true; attribute TAP_SCAN_RESET of TRST_ : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56305 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56305 : entity is "EXTEST (0000)," & "SAMPLE (0001),"...

  • Page 595

    JTAG BSDL "ENABLE_ONCE (0110)," & "DEBUG_REQUEST (0111)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of DSP56305 : entity is "0001"; attribute IDCODE_REGISTER of DSP56305 : entity is "0000" & -- version "000110" & -- manufacturer’s use "0000000101" & -- sequence number "00000001110"...

  • Page 596

    "73 (BC_6, D(19), bidir, Z)," & "74 (BC_6, D(20), bidir, Z)," & "75 (BC_6, D(21), bidir, Z)," & "76 (BC_6, D(22), bidir, Z)," & "77 (BC_6, D(23), bidir, Z)," & "78 (BC_2, IRQA_, input, X)," & DSP56305 User’s Manual MOTOROLA...

  • Page 597

    "122 (BC_6, HIRDY_, bidir, 121, 1, Z)," & "123 (BC_1, *, control, 1)," & "124 (BC_6, HTRDY_, bidir, 123, 1, Z)," & "125 (BC_1, *, control, 1)," & "126 (BC_6, HDEVSEL_, bidir, 125, 1, Z)," & MOTOROLA DSP56305 User’s Manual...

  • Page 598

    (BC_6, HAD(3), bidir, 170, 1, Z)," & "172 (BC_1, *, control, 1)," & "173 (BC_6, HAD(2), bidir, 172, 1, Z)," & "174 (BC_1, *, control, 1)," & "175 (BC_6, HAD(1), bidir, 174, 1, Z)," & C-10 DSP56305 User’s Manual MOTOROLA...

  • Page 599

    (BC_6, SC10, bidir, 211, 1, Z)," & "213 (BC_1, *, control, 1)," & "214 (BC_6, SC20, bidir, 213, 1, Z)," & "215 (BC_1, *, control, 1)," & "216 (BC_6, DE_, bidir, 215, 1, Z)"; end DSP56305; MOTOROLA DSP56305 User’s Manual C-11...

  • Page 600

    JTAG BSDL C-12 DSP56305 User’s Manual MOTOROLA...

  • Page 601: Appendix D Programming Reference

    APPENDIX D PROGRAMMING REFERENCE MOTOROLA DSP56305 User’s Manual...

  • Page 602

    PROGRAMMING REFERENCE DSP56305 User’s Manual MOTOROLA...

  • Page 603: D.1 Introduction, D.1.1 Peripheral Addresses, D.1.2 Interrupt Addresses, D.1.3 Interrupt Priorities, D.1.4 Dma Requests

    D.1.4 DMA Requests Table D-4 lists the DMA requests. D.1.5 Programming Sheets Figures describing the major programmable registers on the DSP56305. D.1.6 HI32 Registers — Quick Reference Tables Table D-5 provides a handy reference tool for the HI32 Registers. MOTOROLA...

  • Page 604: D.2 Internal I/o Memory Map

    DMA Offset Register 2 (DOR2) $FFF0 $FFFFF0 DMA Offset Register 3 (DOR3) DMA0 $FFEF $FFFFEF DMA Source Address Register (DSR0) $FFEE $FFFFEE DMA Destination Address Register (DDR0) $FFED $FFFFED DMA Counter (DCO0) $FFEC $FFFFEC DMA Control Register (DCR0) DSP56305 User’s Manual MOTOROLA...

  • Page 605

    $FFFFDD DMA Counter (DCO4) $FFDC $FFFFDC DMA Control Register (DCR4) DMA5 $FFDB $FFFFDB DMA Source Address Register (DSR5) $FFDA $FFFFDA DMA Destination Address Register (DDR5) $FFD9 $FFFFD9 DMA Counter (DCO5) $FFD8 $FFFFD8 DMA Control Register (DCR5) MOTOROLA DSP56305 User’s Manual...

  • Page 606

    Host Receive Register (HRX) $FFC5 $FFFFC5 Host Base Address Register (HBAR) $FFC4 $FFFFC4 Host Polarity Control Register (HPCR) $FFC3 $FFFFC3 Host Status Register (HSR) $FFC2 $FFFFC2 Host Control Register (HCR) $FFC1 $FFFFC1 Reserved $FFC0 $FFFFC0 Reserved DSP56305 User’s Manual MOTOROLA...

  • Page 607

    $FFFFB1 ESSI 0 Receive Slot Mask Register B (RSMB0) $FFB0 $FFFFB0 Reserved PORT D $FFAF $FFFFAF Port D Control Register (PCRD) $FFAE $FFFFAE Port D Direction Register (PRRD) $FFAD $FFFFAD Port C GPIO Data Register (PDRD) MOTOROLA DSP56305 User’s Manual...

  • Page 608

    $FFFFA1 ESSI 1 Receive Slot Mask Register B (RSMB1) $FFA0 $FFFFA0 Reserved PORT E $FF9F $FFFF9F Port E Control Register (PCRE) $FF9E $FFFF9E Port E Direction Register (PRRE) $FF9D $FFFF9D Port E GPIO Data Register (PDRE) DSP56305 User’s Manual MOTOROLA...

  • Page 609

    SCI Transmit Data Register - Middle (STXM) $FF95 $FFFF95 SCI Transmit Data Register - Low (STXL) $FF94 $FFFF94 SCI Transmit Address Register (STXA) $FF93 $FFFF93 SCI Status Register (SSR) $FF92 $FFFF92 Reserved $FF91 $FFFF91 Reserved $FF90 $FFFF90 Reserved MOTOROLA DSP56305 User’s Manual...

  • Page 610

    Timer 2 Load Register (TLR2) $FF85 $FFFF85 Timer 2 Compare Register (TCPR2) $FF84 $FFFF84 Timer 2 Count Register (TCR2) $FF83 $FFFF83 Timer Prescaler Load Register (TPLR) $FF82 $FFFF82 Timer Prescaler Count Register (TPCR) $FF81 $FFFF81 Reserved $FF80 $FFFF80 Reserved D-10 DSP56305 User’s Manual MOTOROLA...

  • Page 611: D.3 Interrupt Addresses And Sources

    TIMER 1 Overflow VBA:$2C 0–2 TIMER 2 Compare VBA:$2E 0–2 TIMER 2 Overflow VBA:$30 0–2 ESSI0 Receive Data VBA:$32 0–2 ESSI0 Receive Data With Exception Status VBA:$34 0–2 ESSI0 Receive Last Slot VBA:$36 0–2 ESSI0 Transmit Data MOTOROLA DSP56305 User’s Manual D-11...

  • Page 612

    0–2 SCI Timer VBA:$5A 0–2 Reserved VBA:$5C 0–2 Reserved VBA:$5E 0–2 Reserved VBA:$60 0–2 Host Receive Data Full VBA:$62 0–2 Host Transmit Data Empty VBA:$64 0–2 Host Command (Default) VBA:$66 0–2 Reserved VBA:$FE 0–2 Reserved D-12 DSP56305 User’s Manual MOTOROLA...

  • Page 613: D.4 Interrupt Priorities

    DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 RX Data with Exception Interrupt MOTOROLA DSP56305 User’s Manual D-13...

  • Page 614

    SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line SCI Timer TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt Lowest TIMER2 Compare Interrupt D-14 DSP56305 User’s Manual MOTOROLA...

  • Page 615: D.5 Dma Request Sources

    Timer1 (TCF1=1) 10010 Timer2 (TCF2=1) 10011 FCOP Data Input Buffer Empty (FDIBE=1) 10100 FCOP Data Output Buffer Full (FDOBF=1) 10101 VCOP Input Data (DREQ=1) 10110 VCOP Output Buffer Full (DOBF=1) 10111 VCOP Output Data (DRDY=1) MOTOROLA DSP56305 User’s Manual D-15...

  • Page 616: D.6 Programming Reference Sheets

    Host Master Transmit Data (MTRQ=1) PROGRAMMING REFERENCE SHEETS On the following pages, Figure D-1, Status Register (SR) through Figure D-25, Port E Registers (PCRE, PRRE, PDRE) provide a set of programming reference sheets for the DSP56305 registers. D-16 DSP56305 User’s Manual MOTOROLA...

  • Page 617

    15 14 13 12 11 10 9 Extended Mode Register (MR) Mode Register (MR) Condition Code Register (CCR) Status Register (SR) = Reserved, Program as 0 Read/Write Reset = $C00300 Figure D-1 Status Register (SR) MOTOROLA DSP56305 User’s Manual D-17...

  • Page 618

    Status Register (SCS) Mode Register (COM) Register (COM) Operating Mode Register (OMR) = Reserved, Program as 0 Read/Write X = Latched from levels on Mode pins Reset = $00030X Figure D-2 Operating Mode Register (OMR) D-18 DSP56305 User’s Manual MOTOROLA...

  • Page 619

    PROGRAMMING REFERENCE Date: Application: Programmer: Sheet 3 of 5 Figure D-3 Interrupt Priority Register–Core (IPR–C) MOTOROLA DSP56305 User’s Manual D-19...

  • Page 620

    CENTRAL PROCESSOR ESSI1 IPL Host IPL S1L1 S1L0 Enabled HPL1 HPL0 Enabled — — Timer IPL SCI IPL ESSI0 IPL TOL1 TOL0 Enabled SCL1 SCL0 Enabled S0L1 S0L0 Enabled — — — 23 22 21 20 19 18 15 14 13 12 11 10 9 T0L1 T0L0 SCL1...

  • Page 621

    PROGRAMMING REFERENCE Date: Application: Programmer: Sheet 5 of 5 Figure D-5 Phase Lock Loop Control Register (PCTL) MOTOROLA DSP56305 User’s Manual D-21...

  • Page 622

    15 14 13 12 11 10 9 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data Register (HTX) X:$FFEC7 Write Only Reset = empty Figure D-6 Host Receive and Host Transmit Data Registers D-22 DSP56305 User’s Manual MOTOROLA...

  • Page 623

    0 = ÷ Wait 1 = ÷ Ready Host Flags Read Only HTDE HRDF Host Staus Register (HSR) X:$FFFFC3 Read Only Reset = $2 = Reserved, Program as 0 Figure D-7 Host Control and Host Status Registers MOTOROLA DSP56305 User’s Manual D-23...

  • Page 624: Programming Reference

    HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $0 = Reserved, Program as 0 Figure D-8 Host Base Address and Host Port Control Registers D-24 DSP56305 User’s Manual MOTOROLA...

  • Page 625

    0 = ÷ HREQ Deasserted 1 = ÷ HREQ Asserted HREQ TRDY TXDE RXDF Interrupt Status Register (ISR) $2 Read/Write Reset = $06 = Reserved, Program as 0 Figure D-9 Interrupt Control and Interrupt Status Registers MOTOROLA DSP56305 User’s Manual D-25...

  • Page 626

    Contains Host Command Interrupt Address ÷ 2 Host Command Handshakes Executing Host Command Interrupts Command Vector Register (CVR) Reset = $2A Contains the host command interrupt address Figure D-10 Interrupt Vector and Command Vector Registers D-26 DSP56305 User’s Manual MOTOROLA...

  • Page 627

    Host Transmit Data (usually loaded by program) Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = $00 Figure D-11 Host Receive and Host Transmit Data Registers MOTOROLA DSP56305 User’s Manual D-27...

  • Page 628

    PROGRAMMING REFERENCE Date: Application: Programmer: Sheet 1 of 4 Figure D-12 ESSI Control Register A (CRA) D-28 DSP56305 User’s Manual MOTOROLA...

  • Page 629

    PROGRAMMING REFERENCE Date: Application: Programmer: Sheet 2 of 4 Figure D-13 ESSI Control Register B (CRB) MOTOROLA DSP56305 User’s Manual D-29...

  • Page 630

    Receive Data Register Full 0 = ÷ Wait 1 = ÷ Read SSI Status Register (SSISRx) ESSI0: $FFFFB7 (Read) ESSI1: $FFFFA7 (Read) SSI Status Bits = Reserved, program as 0 Figure D-14 ESSI Status Register (SSISR) D-30 DSP56305 User’s Manual MOTOROLA...

  • Page 631

    RS21 RS20 RS19 RS18 RS17 RS16 RSMBx ESSI0: $FFFFB1 Read/Write ESSI1: $FFFFA1 Read/Write Reset = $FFFF ESSI Receive Slot Mask B = Reserved, Program as 0 Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) MOTOROLA DSP56305 User’s Manual D-31...

  • Page 632

    15 14 13 12 11 10 9 REIE SCKP STIR TMIE ILIE WOMS WAKE SBK SSFTD WDS2 WDS1 WDS0 SCI Control Register (SCR) Address X:$FFFF9C Read/Write = Reserved, Program as 0 SCI Control Register (SCR) Figure D-16 SCI Control Register (SCR) D-32 DSP56305 User’s Manual MOTOROLA...

  • Page 633

    0 = ÷1 1 = ÷ 8 15 14 13 12 11 10 TCM RCM COD CD11 CD10 CD9 = Reserved, Program as 0 SCI Clock Control Register (SCCR) Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR) MOTOROLA DSP56305 User’s Manual D-33...

  • Page 634

    X:$FFFF99 Read Reset = xxxxxx X:$FFFF98 Packing “A” “B” “C” Note: STX is the same register decoded at three different addresses SCI Receive Data Registers Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX) D-34 DSP56305 User’s Manual MOTOROLA...

  • Page 635

    15 14 13 12 11 10 9 Current Value of Prescaler Counter (PC [0:20]) Timer Prescaler Count Register = Reserved, Program as 0 TPCR:$FFFF82 Read Only Reset = $000000 Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR) MOTOROLA DSP56305 User’s Manual D-35...

  • Page 636

    19 18 17 16 15 14 13 12 11 10 9 TRM INV TCIE TQIE Timer Control/Status Register = Reserved, Program as 0 TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset = $000000 Figure D-20 Timer Control/Status Register (TCSR) D-36 DSP56305 User’s Manual MOTOROLA...

  • Page 637

    15 14 13 12 11 10 9 Timer Count Value Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000 Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR) MOTOROLA DSP56305 User’s Manual D-37...

  • Page 638

    DRx = 0 → HIx is Input Host Data Register (HDR) X:$FFFFC9 Write Reset = Undefined DRx holds value of corresponding HI08 GPIO pin. Function depends on HDDR. Figure D-22 Host Data Direction and Host Data Registers (HDDR, HDR) D-38 DSP56305 User’s Manual MOTOROLA...

  • Page 639

    GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-23 Port C Registers (PCRC, PRRC, PDRC) MOTOROLA DSP56305 User’s Manual D-39...

  • Page 640

    GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-24 Port D Registers (PCRD, PRRD, PDRD) D-40 DSP56305 User’s Manual MOTOROLA...

  • Page 641

    GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-25 Port E Registers MOTOROLA DSP56305 User’s Manual D-41...

  • Page 642: D.7 Quick Reference Tables

    PROGRAMMING REFERENCE QUICK REFERENCE TABLES (See Table D-5 HI32 Programming Model - Quick Reference on page D-43.) D-42 DSP56305 User’s Manual MOTOROLA...

  • Page 643

    HIRQ - open drain may be Control HIRQ - driven changed only in PS reset HM2-HM0 HI32 Mode Terminate and Reset may be changed to GenBus non-zero Enhanced GenBus value only in GPIO PS reset Self Configuration Reserved MOTOROLA DSP56305 User’s Manual D-43...

  • Page 644

    HI32 retries accesses after in PS reset write accesses Insert Address Enable HI32 does not insert address may be HI32 inserts address in changed only incoming data in PS reset D-44 DSP56305 User’s Manual MOTOROLA...

  • Page 645

    FIFO is not DRXR is empty emptied by core reads; or the data to be read from the DRXR is master data. HF2-HF0 Host Flags HACT HI32 Active HI32 is in personal reset (PS) HI32 is active MOTOROLA DSP56305 User’s Manual D-45...

  • Page 646

    Complete core writing 1 HI32 has completed transfer of may be data to the core, and will written 1 only disconnect write accesses to if HDTC = 1 the HTXR 21-16 RDC5-RDC Remaining Data Count D-46 DSP56305 User’s Manual MOTOROLA...

  • Page 647

    3 Right, zero ext.2 LSBs 3 Right, sign ext.2 LSBs 3 Left, zero filled2 middle bytes HS2-HS0 Host Semaphores TWSD Target Wait State Disable HI32 target will insert up to 8 w.s. HI32 target will not insert wait states MOTOROLA DSP56305 User’s Manual D-47...

  • Page 648

    Host Master Receive Data empty FIFO HRXS 31- Host Slave Receive Data empty FIFO HTXR 31- Host Transmit Data FIFO empty CVID VID15-VID0 Vendor ID hardwired CDID $1057 DID15-DID0 Device ID via programm able (Section 6.10) D-48 DSP56305 User’s Manual MOTOROLA...

  • Page 649

    1 CRID RID7-RID0 Revision ID via programm CCCR able (Section PI7-PI0 PCI Device Program 6.10) Interface SC7-SC0 PCI Device Sub-Class BC7-BC0 PCI Device Base Class MOTOROLA DSP56305 User’s Manual D-49...

  • Page 650

    PCI interrupt line routing information IL7-IL0 Interrupt Line $01 INTA is supported hardwired MG7-MG0 MAX_GNT $00 Min Grant hardwired ML7-ML0 MAX_LAT $00 Max Latency hardwired STRQ. MTRQ are zero in the personal software reset state. D-50 DSP56305 User’s Manual MOTOROLA...

  • Page 651

    11—Clock Polarity bit (CKP) 7-24 CC00–CC01 bits 10-13 bit 12—Asynchronous/Synchronous bit CC10–CC11 bits 10-14 (SYN) 7-24 CD0–CD11 bits 8-18 bit 13—ESSI Mode Select bit (MOD) 7-27 Central Processing Unit (CPU) 1-3 bit 14—ESSI Transmit 2 Enable bit (TE2) 7-29 MOTOROLA DSP56305 User’s Manual Index-1...

  • Page 652

    ESSI Transmit Slot Mask Registers (TSMA, TSMB) 7-41 ESSI0 (GPIO) 5-3 ENABLE_ONCE instruction 11-11 ESSI1 (GPIO) 5-4 Enhanced Synchronous Serial Interface 2-3 2-29 EX bit 10-6 2-32 Exit Command bit (EX) 10-6 Enhanced Synchronous Serial Interface (ESSI) 1-16 Index-2 DSP56305 User’s Manual MOTOROLA...

  • Page 653

    (GPIO) 5-3 Debug Event signal (DE signal) 10-4 HI32 2-4 2-18 2-19 HI-Z instruction 11-11 Host Inteface 2-3 Host Interface 1-16 2-18 2-19 LA register 1-10 PCI 2-4 LC register 1-10 PCI bus 2-5 logic 1-7 MOTOROLA DSP56305 User’s Manual Index-3...

  • Page 654

    8–9—Breakpoint 1 Condition Code Select OnCE PAB Register for Decode Register bits (CC10–CC11) 10-14 (OPABDR) 10-20 bits 10–11—Breakpoint 0 and 1 Event Select OnCE PAB Register for Execute (OPABEX) 10-21 bits (BT0–BT1) 10-14 reserved bits—bits 12–15 10-15 Index-4 DSP56305 User’s Manual MOTOROLA...

  • Page 655

    Port E Direction Register (PRRE) 8-30 Power 2-6 PAB 1-13 power PAG 1-10 low 1-7 Parity Error bit (PE) 8-16 management 1-7 Patch Mode standby modes 1-7 PEN bit 4-23 PreDivider Factor bits (PD) 4-24 MOTOROLA DSP56305 User’s Manual Index-5...

  • Page 656

    Receiver Overrun Error Flag bit (ROE) 7-37 exceptions 8-29 Receiver Wakeup Enable bit (SBK) 8-11 Idle Line 8-29 Register Select bits (RS0–RS4) 10-6 Receive Data 8-29 REIE bit 7-35 8-14 Receive Data with Exception Status 8-29 reserved bits Timer 8-29 Index-6 DSP56305 User’s Manual MOTOROLA...

  • Page 657

    7—Wired-OR Mode Select bit (WOMS) 8-11 SSFTD bit 8-10 bit 8—Receiver Enable bit (RE) 8-11 SSISR register 7-35 bit 9—Transmitter Enable bit (TE) 8-12 bit 0—Serial Input Flag 0 bit (IF0) 7-35 bit 1—Serial Input Flag 1 bit (IF1) 7-36 MOTOROLA DSP56305 User’s Manual Index-7...

  • Page 658

    Timer Enable bit (TE) 9-10 TCIE bit 9-11 Timer Interrupt Enable bit (TMIE) 8-13 TCK pin 11-5 Timer Interrupt Rate bit (STIR) 8-13 TCM bit 8-20 Timer Load Register (TLR) 9-17 TCPR register 9-17 timer mode Index-8 DSP56305 User’s Manual MOTOROLA...

  • Page 659

    X Memory Data Bus (XDB) 1-13 Trace Mode Enable bit (TME) 10-8 X Memory Expansion Bus 1-13 Trace Occurrence bit (TO) 10-9 XAB 1-13 Transmit 0 Enable bit (TE0) 7-31 XDB 1-13 Transmit 1 Enable bit (TE1) 7-30 MOTOROLA DSP56305 User’s Manual Index-9...

  • Page 660

    XTAL Disable bit (XTLD) 4-24 XTLD bit 4-24 Y data RAM 3-6 Y Memory Address Bus (YAB) 1-13 Y Memory Data Bus (YDB) 1-13 Y Memory Expansion Bus 1-13 YAB 1-13 YDB 1-13 Index-10 DSP56305 User’s Manual MOTOROLA...

  • Page 661

    MOTOROLA DSP56305 User’s Manual Index-11...

  • Page 662

    Index-12 DSP56305 User’s Manual MOTOROLA...

  • Page 663

    MOTOROLA DSP56305 User’s Manual Index-13...

  • Page 664

    Index-14 DSP56305 User’s Manual MOTOROLA...

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