Dsp56100 Core Block Diagram Description - Motorola DSP56156 Manual

ADDRESS
GENERATION
PORT B
UNIT
OR
HOST
ON-CHIP
15
PERIPHERALS
HOST, SSI0,
7+12
SSI1, TIMER
GPI/O, CODEC
CODEC,
PORT C
INTERNAL DATA
AND/OR
BUS SWITCH
SSI0, SSI1,
AND BIT
TIMER MANIPULATION
UNIT
EXTAL
CLOCK
SXFC
AND PLL
CLKO
OnCE
4
Figure 1-2 Detailed RAM Based Part Block Diagram
A general block diagram of the DSP56156 is shown in Figure 1-2 (see Section 3.2 for in-
formation on the ROM based part). The DSP56156 is optimized for applications such as
medium to low bit rate speech encoding but can also be used in many other types of ap-
plications.
Table 1-1 is a list of the DSP56156 primary features. The core features are common to
any product using the DSP56100 CORE processor.
1.2

DSP56100 CORE BLOCK DIAGRAM DESCRIPTION

The heart of the DSP56156 architecture is a 16-bit multiple-bus core processor called the
DSP56100 CORE and designed specifically for real-time digital signal processing (DSP).
The overall architecture is presented here and can be seen in Figure 1-5. For a detailed
description of the core processor, see the DSP56100 Family Manual .
1 - 6

DSP56100 CORE BLOCK DIAGRAM DESCRIPTION

BOOTSTRAP
ROM
64x16
PROGRAM CONTROL UNIT
PROGRAM PROGRAM
ADDRESS DECODE
GENERATOR CONTROLLER
MODC
DSP56156 OVERVIEW
XAB1
XAB2
PAB
DATA
PROGRAM
RAM
RAM
2Kx16
2Kx16
XDB
PDB
GDB
PROGRAM
INTERRUPT 16x16+40 - 40-BIT MAC
CONTROLLER
TWO 40-BIT ACCUMULATORS
MODA/IRQA
MODB/IRQB
RESET
ADDRESS
EXTERNAL
ADDRESS
BUS
16
SWITCH
BUS
8
CONTROL
16
DATA
EXTERNAL
DATA BUS
SWITCH
DATA ALU
16 BITS
MOTOROLA