Prescaler Clock Enable (Pce) — Tcsr Bit 15; Timer Overflow Flag (Tof) — Tcsr Bit 20; Timer Compare Flag (Tcf) — Tcsr Bit 21; Reserved Bits — Tcsr Bits 3, 10, 14, 16-19, 22, 23 - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Architecture
9.3.3.10 Prescaler Clock Enable (PCE) — TCSR Bit 15
The Prescaler Clock Enable (PCE) bit selects which clock is the timer source clock. When
the PCE bit is cleared, the timer uses either an internal (CLK/2) signal or an external
(TIO) signal as its source clock. When the PCE bit is set, the prescaler output is used as
the timer source clock for the counter regardless of the timer operating mode. To ensure
proper operation, the PCE bit should be changed only when the timer is disabled (when
the TE bit is cleared). The source clock used for the prescaler is determined by the PS[1:0]
bits of the TPLR. A timer can be clocked by a prescaler clock derived from the TIO of
another timer.
The PCE bit is cleared by a hardware RESET signal or a software RESET instruction.
9.3.3.11 Timer Overflow Flag (TOF) — TCSR Bit 20
The Timer Overflow Flag (TOF) bit indicates that counter overflow has occurred. This bit
is cleared by writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is
also cleared when the timer overflow interrupt is serviced.
The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
9.3.3.12 Timer Compare Flag (TCF) — TCSR Bit 21
The Timer Compare Flag (TCF) bit is set to indicate that the event count is complete. In
the Timer, PWM, and Watchdog modes, the TCF bit is set when (N – M + 1) events have
been counted. (N is the value in the compare register and M is the TLR value.) In the
Measurement modes, the TCF bit is set when the measurement has been completed.
The TCF bit is cleared by writing a 1 into the TCF bit. Writing a 0 into the TCF bit has no
effect. The bit is also cleared when the timer compare interrupt is serviced.
The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
The TOF and TCF bits are cleared by writing a 1 to that bit. In order to assure
Note:
that only the desired bit is cleared, do not use the BSET command. The proper
way to clear these bits is to write (using a MOVEP instruction) a 1 to the flag to
be cleared and a 0 to the other flag.
9.3.3.13 Reserved Bits — TCSR Bits 3, 10, 14, 16-19, 22, 23
These reserved bits are read as 0 and should be written with 0 for future compatibility.
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