Table 6-1 Hi32 Resets - Motorola DSP56305 User Manual

6.3 HI32 RESETS
The following table lists and describes the resets available in the HI32.
Type
Hardware HS The
Reset
Software
Reset
Personal PS
Software
Reset
STOP ST
Reset
Personal PH The HI32
Hardware
Reset
MOTOROLA

Table 6-1 HI32 Resets

Initiated when
DSP56300
core
RESET signal is
asserted.
The RESET
instruction is
executed.
DSP56300
The core
writes zeros to the
HI32 mode bits
HM[2:0] in the DSP
Control Register or
the HS reset is
executed
The STOP
instruction is
executed.
HRST/HRST signal
is asserted.
DSP56305 User's Manual
Description
These resets force the HI32 DSP side state
machines, control and status registers to their
initial states.
These resets also activate the Personal Software
(PS) reset (see below).
The HI32 terminates the current PCI transaction (if
it is an active PCI agent), clears the HACT bit in the
DSP Status Register (DSR) and enters the personal
software (PS) reset state. All data paths are cleared,
as are some status register bits.
In the personal software reset state, the HI32 is a
PCI agent and will respond to all memory space
transactions with a retry event. If connected to
other buses (e.g., the ISA bus,
based DSP Port A bus, etc.) all outputs are high
impedance.
This reset forces all host port signals to the
disconnected state: all outputs are high impedance,
all inputs are electrically disconnected.
The host port signals are affected immediately.
Note: This reset may be executed only when the
HACT bit in the DSP Status Register (DSR) is
zero.
This reset forces the HI32 host side state machines,
control registers, FIFOs, and configuration
registers to their initial states. All host port signals,
except HRST/HRST, are forced to the
disconnected state: all outputs are high impedance,
inputs are electrically disconnected. The DSP side
state machines are not affected.
The HRST/HRST signal is ignored in the self
configuration mode.
HOST INTERFACE (HI32)
HI32 Resets
DSP56300
core
6-9