Table 4-4 Interrupt Source Priorities Within An Ipl - Motorola DSP56305 User Manual

24-bit digital signal processor
Table of Contents

Advertisement

Core Configuration
Interrupt Sources and Priorities

Table 4-4 Interrupt Source Priorities within an IPL

Priority
Highest
Lowest
Highest
4-18
Level 3 (Nonmaskable)
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Non-Maskable Interrupt
Non-Maskable Host Command Interrupt
Levels 0, 1, 2 (Maskable)
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
Host Command Interrupt
Host PCI Transaction Termination
Host PCI Transaction Abort
Host PCI Parity Error
Host PCI Transfer Complete
Host PCI Master Receive Request
Host Slave Receive Request
DSP56305 User's Manual
Interrupt Source
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents