Transmitter Enable (Te) Scr Bit 9; Idle Line Interrupt Enable (Ilie) Scr Bit 10 - Motorola DSP56305 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
8.3.1.8

Transmitter Enable (TE) SCR Bit 9

When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes
transmission of data in the SCI Transmit Data Shift Register, then the serial output is
forced high (i.e., idle). Data present in the SCI Transmit Data Register (STX) is not
transmitted. STX may be written and TDRE cleared, but the data is not transferred into
the shift register. TE does not inhibit TDRE or transmit interrupts. TE is cleared by
hardware and software reset.
Setting TE causes the transmitter to send a preamble of ten or eleven consecutive 1s
(depending on WDS). This procedure gives the programmer a convenient way to ensure
that the line goes idle before starting a new message. To force this separation of
messages by the minimum idle line time, the following sequence is recommended:
1. Write the last byte of the first message to STX.
2. Wait for TDRE to go high, indicating the last byte has been transferred to the
Transmit Shift Register.
3. Clear TE and set TE. This queues an idle line preamble to follow immediately the
transmission of the last character of the message (including the stop bit).
4. Write the first byte of the second message to STX.
In this sequence, if the first byte of the second message is not transferred to STX prior to
the finish of the preamble transmission, the transmit data line marks idle until STX is
finally written.
8.3.1.9

Idle Line Interrupt Enable (ILIE) SCR Bit 10

When ILIE is set, the SCI interrupt occurs when IDLE (SSR Bit 3) is set. When ILIE is
cleared, the IDLE interrupt is disabled. ILIE is cleared by hardware and software reset.
An internal flag, the Shift Register Idle Interrupt (SRIINT) flag, is the interrupt request to
the interrupt controller. SRIINT is not directly accessible to the user.
When a valid start bit has been received, an idle interrupt is generated if both IDLE and
ILIE are set. The idle interrupt acknowledge from the interrupt controller clears this
interrupt request. The idle interrupt is not asserted again until at least one character has
been received. The results are as follows:
1. The IDLE bit shows the real status of the receive line at all times.
2. An idle interrupt is generated once for each idle state, no matter how long the idle
state lasts.
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