Pll Control Register; Pll Multiplication Factor (Mf11:0)—Pctl Bits 0–11; Crystal Range (Xtlr)—Pctl Bit 15; Figure 4-3 Dsp56305 Operating Mode Register (Omr) - Motorola DSP56305 User Manual

SCS
23 22 21 20 19 18
SEN WRP EOV EUN XYS ATE
SEN—Stack Extension Enable
WRP—Extended Stack Wrap Flag
EOV—Extended Stack Overflow Flag
EUN—Extended Stack Underflow Flag
XYS—Stack Extension Space Select
ATE—Address Tracing Enable
Reserved bit. Read as zero, should be written with zero for future compatibility.
Reserved for internal use. Should be written with zero for proper operation.

Figure 4-3 DSP56305 Operating Mode Register (OMR)

4.8

PLL CONTROL REGISTER

The PLL Control register (PCTL) is an X-I/O mapped, 24-bit read/write register used to
direct the operation of the on-chip PLL. The PCTL control bits are shown in Figure 4-4.
Refer to the DSP56300 Family Manual for a full description of the PCTL.
11 10
MF11 MF10
23 22
PD3 PD2
4.8.1 PLL Multiplication Factor (MF11:0)—PCTL Bits 0–11
The Multiplication Factor bits (MF[11:0]) define the Multiplication Factor (MF) that is
applied to the PLL input frequency. The MF bits are cleared during DSP56305 hardware
reset, which corresponds to an MF of one.
4.8.2 Crystal Range (XTLR)—PCTL Bit 15
The Crystal Range bit (XTLR) controls the on-chip crystal oscillator transconductance. It
is cleared during hardware reset.
MOTOROLA
17 16 15 14 13
BRT TAS BE
BRT—Bus Release Timing
TAS—TA Synchronize Select
BE—Burst Mode Enable
CDP1—Core-DMA Priority 1
CDP0—Core-DMA Priority 0
MS—Memory Switch Mode
9 8 7 6
MF9 MF8 MF7 MF6
21 20 19 18
PD1 PD0 COD PEN

Figure 4-4 PLL Control Register (PCTL)

DSP56305 User's Manual
EOM
12 11 10 9 8 7
CDP1:0 MS SD
SD—Stop Delay
EBD—External Bus Disable
MD—Operating Mode D
MC—Operating Mode C
MB—Operating Mode B
MA—Operating Mode A
5 4 3
MF5 MF4 MF3
17 16 15
PSTP XTLD XTLR
Core Configuration
PLL Control Register
COM
6 5 4 3 2 1
EBD MD MC MB MA
AA0851
2 1 0
MF2 MF1 MF0
14 13 12
DF2 DF1 DF0
AA0852
0
4-23