Y Data Memory Space; Table 3-1 Memory Space Configuration Bit Settings For The Dsp56305 - Motorola DSP56305 User Manual

Memory Configuration
Memory Spaces
3.1.2.2

Y Data Memory Space

The on-chip Y data RAM is 24-bit wide, high-speed, internal Static RAM occupying the
lowest 2048 (2 K) locations ($000000–$0007FF) in Y memory space. It is organized in 8
banks with 256 locations each.
The on-chip Y data ROM is a 24-bit wide, internal, read-only, static memory occupying
3072 (3 K) locations ($FF0000–$FF0BFF) in Y memory space. It is organized in 12 banks
with 256 locations each.
Some of the on-chip peripheral registers occupy 64 locations ($FFFF80–$FFFFBF) in Y
data memory. This area is called internal Y-I/O space and it can be accessed by the
MOVE or MOVEP instructions and by bit-oriented instructions (BCHG, BCLR, BSET,
BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET).
The off-chip peripheral registers should be mapped into the top 64 locations
($FFFFC0–$FFFFFF) to take advantage of the move peripheral data (MOVEP) instruction
and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR,
BSSET, JCLR, JSET, JSCLR and JSSET). This area is called external Y-I/O space.
For a listing of the contents of internal and external Y-I/O space, see the Programming
Sheets in Appendix D.
The Y memory space at locations $FF0C00–$FFEFFF is reserved and should not be
accessed.
3.1.3 Memory Space Configuration
Memory space addressing is for 24-bit words by default. The DSP56305 switches to
Sixteen-bit Address Compatibility mode by setting the Sixteen-bit Compatibility (SC) bit
in the Status Register (SR).

Table 3-1 Memory Space Configuration Bit Settings for the DSP56305

Bit Cleared = 0
Bit Name Bit Location Set = 1 Effect
Abbreviation Effect (Default)
SC Sixteen-bit SR 13 16 M word 64 K word
Compatibility address space address space
(24-bit word) (16-bit word)
Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-8.
3-6 DSP56305 User's Manual MOTOROLA