Sci Receive Interrupt Enable (Rie) Scr Bit 11; Sci Transmit Interrupt Enable (Tie) Scr Bit 12; Timer Interrupt Enable (Tmie) Scr Bit 13; Timer Interrupt Rate (Stir) Scr Bit 14 - Motorola DSP56305 User Manual

8.3.1.10

SCI Receive Interrupt Enable (RIE) SCR Bit 11

The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive
Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be
polled to determine if the Receive Data Register is full. If both RIE and RDRF are set, the
SCI requests an SCI Receive Data interrupt from the interrupt controller.
Receive interrupts with exception have higher priority than normal Receive Data
interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set,
the SCI requests an SCI Receive Data with Exception interrupt from the interrupt
controller. RIE is cleared by hardware and software reset.
8.3.1.11

SCI Transmit Interrupt Enable (TIE) SCR Bit 12

The TIE bit is set to enable the SCI Transmit Data interrupt. If TIE is cleared, Transmit
Data interrupts are disabled, and the Transmit Data Register Empty (TDRE) bit in the
SSR must be polled to determine if the Transmit Data Register is empty. If both TIE and
TDRE are set, the SCI requests an SCI Transmit Data interrupt from the interrupt
controller. TIE is cleared by hardware and software reset.
8.3.1.12

Timer Interrupt Enable (TMIE) SCR Bit 13

The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt
requests are sent to the interrupt controller at the rate set by the SCCR. The timer
interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt
controller. This feature allows DSP programmers to use the SCI baud rate generator as a
simple periodic interrupt generator if the SCI is not in use, if external clocks are used for
the SCI, or if periodic interrupts are needed at the SCI baud rate. The SCI internal clock is
divided by 16 (to match the 1
does not require that any SCI signals be configured for SCI use to operate. TMIE is
cleared by hardware and software reset.
8.3.1.13

Timer Interrupt Rate (STIR) SCR Bit 14

The STIR bit controls a divide by 32 in the SCI Timer interrupt generator. When STIR is
cleared, the divide by 32 is inserted in the chain. When STIR is set, the divide by 32 is
bypassed, thereby increasing timer resolution by a factor of thirty-two. This bit is cleared
by hardware and software reset. To ensure proper operation of the timer, STIR must not
be changed during timer operation (i.e., if TMIE = 1).
MOTOROLA
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SCI baud rate) for timer interrupt generation. This timer
DSP56305 User's Manual
Serial Communication Interface (SCI)
SCI Programming Model
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