Trellis; Data Control; Receive Quality Error; Figure 13-5 Bit Error Count Function - Motorola DSP56305 User Manual

13.3.6

Trellis

The Trellis block manages the path history of every path of the trellis associated with
every state in the trellis. The block also provides the hardware required to read the
survivor's hard decision decoded data from the Viterbi. The trellis RAM modules store
the actual decoded data bits (not the pointers). The pass over the trellis states is done in
parallel to the pass over the path metrics. The decision depth of the algorithm is fixed at
36 bits (more than five times the maximum constraint length of seven), implemented
using Trellis RAM (64 × 36 bits).
13.3.7

Data Control

The Data Control block provides control data output flow during decoding, encoding,
and equalization. The block generates interrupts and DMA triggers whenever data is
ready to be read out of the VCOP according to the interrupt modes. The hardware
consists of a 1023 × 1-bit or 64 × 16-bit output buffer used in decoding, encoding, and
equalization.
13.3.8

Receive Quality Error

The Receive Quality Error block supplies information on the quality of the received
block of data. This information is used only in the decoding mode. The block calculates
the Bit Error (BER) count by re-encoding the hard decision data produced by the trellis
block and comparing it with the hardened input symbols. The value obtained is the
number of symbol bits corrected by the decoder. The block supports puncture codes, by
not counting neutral value symbols (e.g., $000000). The BER is available to the DSP56300
core processor via the VBER.
Note: The BER value is true only if the data was successfully decoded, so the
decoding should be checked using CRC.
Soft
Symbol
Hard
Symbol
MOTOROLA
Viterbi
Algorithm
Delay

Figure 13-5 Bit Error Count Function

DSP56305 User's Manual
VITERBI CO-PROCESSOR
Encoder
xor
BER Count
Block Description
AA1315
13-9