Input Buffer Empty Bit (Inbe)—Ccsr Bit 19; Input Fifo Empty Bit (Infe)—Ccsr Bit 20; Output Fifo Not Empty Bit (Ofne)—Ccsr Bit 21; Cipher Done Bit (Cidn)—Ccsr Bit 22 - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
Bit 23, is set). If both PDIE and PCDN bits are set, the CCOP requests a Parity Coding
Done interrupt request from the interrupt controller. When PDIE is cleared, the interrupt
is disabled.
14.4.4.11 Input Buffer Empty bit (INBE)—CCSR Bit 19
The read-only status bit Input Buffer Empty (INBE), when set, indicates that the whole
input path is empty and there are no more data bits to be sent to the CFSRs. INBE is set
when the input FIFO is empty and the shift register/buffer (containing the last FIFO
word) has shifted out all its contents to the CFSRs but yet the Input Counter has not
reached zero, or when the continuous mode is being used (CM bit is set). In this situation
CCOP ceases processing waiting for new data to be input, or the programmer can
explicitly clear PREN causing normal completion of the processing. INBE is cleared after
a data word has been written to the FIFO. INBE does not generate any interrupt. INBE is
set by hardware, software, or CCOP individual reset.
14.4.4.12 Input FIFO Empty bit (INFE)—CCSR Bit 20
The read-only status bit Input FIFO Empty (INFE), when set, indicates that the Data
FIFO Register (CDFR), while operating as the input FIFO, is empty and can be written by
the DSP56300 core. CDFR operates as the input FIFO when CCOP is in the Idle state and
data is expected to be input to FIFO, or when CCOP is in the input or run phase. INFE is
set when the last word of the input FIFO is transferred to the shift register for shifting
into the CFSRs, emptying the input FIFO. It is possible to write up to five data words
(the FIFO depth) each time the INFE is set. INFE is cleared after a data word has been
written to the FIFO. INFE is set by hardware, software, or CCOP individual reset.
14.4.4.13 Output FIFO Not Empty bit (OFNE)—CCSR Bit 21
The read-only status bit Output FIFO Not Empty (OFNE), when set, indicates that the
Data FIFO Register (CDFR), while operating as the output FIFO, has at least one data
word which is ready to be read by the DSP56300 core. CDFR operates as the output FIFO
when CCOP is in the output phase or when CCOP is in the Idle state and data is
expected to be read from FIFO. OFNE is set when the output FIFO is not empty. OFNE is
cleared when the CDFR is read by the DSP56300 core reducing the number of words in
the output FIFO to zero. Since output data bits are written to CDFR in the output phase
only, OFNE is only operational in the Cipher modes (OPM1 = 0) and when CM,CCNT
Bit 23, is cleared. OFNE is cleared by hardware, software, or CCOP individual reset.
14.4.4.14 Cipher Done bit (CIDN)—CCSR Bit 22
The read-only status bit Cipher Done (CIDN), when set, indicates that the Cipher
processing on the input data block was terminated. CIDN is enabled when CCOP
operates in the Cipher modes (OPM1 = 0) and is disabled otherwise. CIDN is set when
the CCOP has completed all phases of the processing (i.e Input, Run, and Output
phases) and all output data has been transferred to the FIFO. If CIDN and CDIE are set, a
Cipher Done interrupt is generated. CIDN is cleared after reading (via CDFR) all the
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