Once Pab Register For Execute (Opabex); Trace Buffer - Motorola DSP56305 User Manual

10.9.3

OnCE PAB Register for Execute (OPABEX)

The OnCE PAB Register for Execute (OPABEX) is a 16-bit register that stores the address
of the instruction currently in the Instruction Latch. This is the instruction that would
have been decoded and executed if the chip would not have entered the Debug mode.
The OPABEX register can only be read through the JTAG port. This register is not
affected by the operations performed during the Debug mode.
10.9.4

Trace Buffer

The Trace buffer stores the addresses of the last twelve change of flow instructions that
were executed, as well as the address of the last executed instruction. The Trace buffer is
implemented as a circular buffer containing twelve 17-bit registers and one 4-bit counter.
All the registers have the same address, but any read access to the Trace buffer address
causes the counter to increment, thus pointing to the next Trace buffer register. The
registers are serially available to the external command controller through their common
Trace buffer address. Figure 10-10 on page 10-22 shows the block diagram of the Trace
buffer. The Trace buffer is not affected by the operations performed during the Debug
mode except for the Trace buffer pointer increment when reading the Trace buffer.
When entering the Debug mode, the Trace buffer counter is pointing to the Trace buffer
register containing the address of the last executed instructions. The first Trace buffer
read obtains the oldest address and the following Trace buffer reads get the other
addresses from the oldest to the newest, in order of execution.
Notes: 1. To ensure Trace buffer coherence, a complete set of twelve reads of the
Trace buffer must be performed. This is necessary due to the fact that each
read increments the Trace buffer pointer, thus pointing to the next
location. After twelve reads, the pointer indicates the same location as
before starting the read procedure.
2. On any change of flow instruction, the Trace buffer stores both the address
of the change of flow instruction, as well as the address of the target of the
change of flow instruction. In the case of conditional change of flows, the
address of the change of flow instruction is always stored (regardless of the
fact that the change of flow is true or false), but if the conditional change of
flow is false (i.e., not taken) the address of the target is not stored. In order
to facilitate the program trace reconstruction, every Trace buffer location
has an additional 'invalid bit' (the 25th bit). If a conditional change of flow
instruction has a 'condition false', the invalid bit is set, thus marking this
instruction as not taken. Therefore, it is imperative to read seventeen bits of
MOTOROLA DSP56305 User's Manual
On-Chip Emulation Module
Trace Buffer
10-21