Table 6-2 Hi32 Programming Model - Dsp Side Registers - Motorola DSP56305 User Manual

6.5 DSP SIDE PROGRAMMING MODEL
The DSP56300 core views the HI32 as a memory-mapped peripheral occupying 11 24-bit
words in data memory space. The HI32 DSP side programming model is shown in
Table 6-2.

Table 6-2 HI32 Programming Model - DSP Side Registers

Address (HI32 via
programmed base
address)
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
The separate host-to-DSP and DSP-to-host data paths FIFOs allow the HI32 and the host
processor to transfer data efficiently at high speeds.
Memory mapping allows DSP56300 core data transfers with the HI32 registers using
standard instructions and addressing modes. In addition, the MOVEP instruction allows
HI32-to-memory and memory-to-HI32 data transfers without going through an
intermediate register.
The on-chip general purpose DMA channels in the DSP56300 core can be programmed
to transfer data between the HI32 data FIFOs and other DMA accessible resources at
maximum throughput, without DSP56300 core intervention.
The DSP56300 core accesses the HI32 using standard polling, interrupt, or DMA
techniques. The following paragraphs describe the purpose and operation of each bit in
each register of the HI32 visible to the DSP56300 core. The effects of different reset types
on these registers are shown.
The HI32 host side programming model is described in Section 6.6.
MOTOROLA
Register
Acronym
DCTR DSP Control Register
DPCR DSP PCI Control Register
DPMC DSP PCI Master Control Register
DPAR DSP PCI Address Register
DSR DSP Status Register
DPSR DSP PCI Status Register
DTXM DSP Master Transmit Data FIFO
DRXR DSP Receive Data FIFO
DTXS DSP Slave Transmit Data FIFO
DIRH DSP GPIO Direction Register
DATH DSP GPIO Data Register
DSP56305 User's Manual
DSP SIDE Programming Model
Register Name
HOST INTERFACE (HI32)
Register Type
Internal I/O space
registers
GPIO registers
6-11