Program Ram; Bootstrap Rom - Motorola DSP56305 User Manual

Memory Configuration
Memory Spaces
The Program ROM usually contains the Real Time Operating System (RTOS), but may
contain customer-supplied code. For further information on supplying code for a
customized DSP56305 Program ROM, please contact your Motorola regional sales office.
Program memory space at locations $FF00C0–$FF07FF and $FF2000–$FFFFFF is
reserved and should not be accessed.
3.1.1.1

Program RAM

The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 6.5 K (default), 5.5 K, or 7.5 K locations in the program memory
space (depending on the settings of the MS and CE bits). The Program RAM default
organization is four banks of 256 24-bit words (1 K). The upper four banks of X data
RAM can be configured as Program RAM by setting the MS bit. When the CE bit is set,
the upper 1 K of Program RAM is used as an internal Instruction Cache.
The Memory Switch bit (OMR Bit 7), when set, switches the uppermost 1 K of X data
RAM to Program RAM.
While the contents of Program RAM are unaffected by toggling the
MS bit, the location of program data placed in the Program
RAM/Instruction Cache area changes after the MS bit is toggled,
since the cache always occupies the top-most 1 K Program RAM
addresses. To preserve program data integrity, do not set or clear
the MS bit when the CE bit is set. See Section 3.2 for the correct
procedure.
3.1.1.2

Bootstrap ROM

The bootstrap code is accessed at addresses $FF0000–$FFF0BF (192 words) in Program
memory space. The bootstrap ROM cannot be accessed in Sixteen-bit Compatibility
mode. See Appendix A for a complete listing of the bootstrap code.
3-4
CAUTION
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