Motorola DSP56305 User Manual page 340

Serial Communication Interface (SCI)
Operating Modes
Register
Bit Mnemonic
Mnemonic
SCCR
CD[11:0]
SRX SRX [23:0]
STX STX[23:0]
SRSH SRS[8:0]
STSH STS[8:0]
Note: 1. SRSH—SCI Receive Shift Register, STSH — SCI Transmit Shift Register
2. HW—Hardware reset is caused by asserting the external RESET signal.
3. SW—Software reset is caused by executing the RESET instruction.
4. IR—Individual reset is caused by clearing PCRE (bits 0–2) (configured for
5. ST—Stop reset is caused by executing the STOP instruction.
6. 1—The bit is set during this reset.
7. 0—The bit is cleared during this reset.
8. — — The bit is not changed during this reset
8-26
Table 8-3 SCI Registers after Reset (Continued)
Bit Number
TRNE 0
TCM 15
RCM 14
SCP 13
COD 12
11–0
23–16, 15–8, 7–0
23–0
8–0
8–0
DSP56305 User's Manual
Reset Type
HW SW
Reset Reset Reset
1 1
0 0
0 0
0 0
0 0
0 0
— —
— —
— —
— —
IR ST
Reset
1 1
— —
— —
— —
— —
— —
— —
— —
— —
— —
GPIO
).
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