Motorola DSP56305 User Manual page 645

HI32 Registers - Quick Reference (Sheet 3 of 8)
Reg Bit #
Mnemonic Name
DPMC 15- AR31-AR16 DSP PCI Transaction
0 Address (High)
21- BL5-BL0 PCI Data Burst Length
16
23- FC1-FC0 Data Transfer Format
22 Control
DPAR 15- AR15-AR0 DSP PCI Transaction
0 Address (Low)
19- C3-C0 PCI Bus Command
16
23- BE3-BE0 PCI Byte Enables
20
DSR HCP Host Command Pending
STRQ Slave Transmit Data
Request
SRRQ Slave Receive Data Request 0
HF2-HF0 Host Flags
HACT HI32 Active
MOTOROLA
Val Function
Transmit Receive
00 32 bit mode32 bit mode
01 3 Right, zero ext.3 LSBs
10 3 Right, sign ext.3 LSBs
11 3 Left, zero filled3 MSBs
0 no host command pending
1 host command pending
1 slave transmit FIFO is not full
0 slave transmit FIFO is full
slave receive FIFO is empty
1 slave receive FIFO is not
empty
0 HI32 is in personal reset (PS)
1 HI32 is active
DSP56305 User's Manual
PROGRAMMING REFERENCE
Comments
may be
written only if
MARQ = 1
may be
written only if
MARQ = 1
may be
written only if
MARQ = 1
may be
written only if
MARQ = 1
may be
written only if
MARQ = 1
may be
written only if
MARQ = 1
cleared when
the HC
interrupt
request is
serviced
cleared if the
DTXS is filled
by core writes
cleared if the
DRXR is
emptied by
core reads; or
the data to be
read from the
DRXR is
master data.
Reset Type
HS PH PS
$0000 - -
$0 - -
$0 - -
$0000 - -
$0 - -
$0 - -
- - 0
a - (a
1 1
0 - 0
- $0 -
0 - 0
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