Table 11-2 Dsp56305 Boundary Scan Register (Bsr) Bit Definitions - Motorola DSP56305 User Manual

The DSP56300 core features a low-power Stop mode, which is invoked using the STOP
instruction. The interaction of the JTAG interface with low-power Stop mode is as
follows:
1. The TAP controller must be in the Test-Logic-Reset state to either enter or remain
in the low-power Stop mode. Leaving the TAP controller Test-Logic-Reset state
negates the ability to achieve low-power, but does not otherwise affect device
functionality.
2. The TCK input is not blocked in low-power Stop mode. To consume minimal
power, the TCK input should be externally connected to V
3. The TMS and TDI signals include on-chip pullup resistors. In low-power Stop
mode, these two signals should remain either unconnected or connected to V
achieve minimal power consumption.
Since during Stop mode all DSP56305 core clocks are disabled, the JTAG interface
provides the means of polling the device status (sampled in the Capture-IR state).
11.5 DSP56305 BOUNDARY SCAN REGISTER
Table 11-2 describes the DSP56305 Boundary Scan Register (BSR) contents.

Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions

Bit #
MOTOROLA
Pin Name
0 IRQA
1 IRQB
2 IRQC
3 IRQD
4 D23
5 D22
6 D21
7 D20
8 D19
9 D18
DSP56305 User's Manual
DSP56305 Boundary Scan Register
Pin Type BSR Cell Type
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
JTAG Port
or GND.
CC
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
to
CC
11-13