Block Description; Figure 13-3 Vcop Block Diagram - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR

Block Description

13.3 BLOCK DESCRIPTION
The Viterbi Co-Processor is composed of the following main functional blocks:
Peripheral Module Bus (PMB) Interface, Flow Control, Branch Metric,
Add-Compare-Select (ACS), Window Error Detection (WED), Trellis, Data Control, and
Receive Quality Error.
PMB (Peripheral Module Bus)
CLK
RESET
DMA ACCESS SIGNALS
INTERRUPT SIGNALS
CORE ACCESS SIGNALS
16
Branch
Metric
32
VP
RAM
16
Delay
DELAY
13-6
PMB Interface
vcra,vcrb,vtrs,vwes,vber
6
Controls
Addr
Addr
ACS
2 × 17
brma,b
Metric
RAM
16
wed 16
WED
Addr
WED
RAM
Receive
Quality
Convolutional
Encoder

Figure 13-3 VCOP Block Diagram

DSP56305 User's Manual
Start
Addr Mode
stg_end
Flow
Control
Trellis
tab_survivor
Trellis
RAM
16
Data Control
Output Buff
surv. bit
63 × 16 bit /
1023 × 1 bit
AA1313
MOTOROLA