Sci Clock Polarity (Sckp) Scr Bit 15; Reie) Scr Bit 16; Sci Status Register (Ssr); Transmitter Empty (Trne) Ssr Bit 0 - Motorola DSP56305 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
8.3.1.14

SCI Clock Polarity (SCKP) SCR Bit 15

The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK),
eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is
positive; when SCKP is set, the clock polarity is negative. In the Synchronous mode,
positive polarity means that the clock is normally positive and transitions negative
during valid data. Negative polarity means that the clock is normally negative and
transitions positive during valid data. In the Asynchronous mode, positive polarity
means that the rising edge of the clock occurs in the center of the period that data is
valid. Negative polarity means that the falling edge of the clock occurs during the center
of the period that data is valid. SCKP is cleared on hardware and software reset.
8.3.1.15 SCI Receive with Exception Interrupt Enable (REIE) SCR Bit 16
The REIE bit is set to enable the SCI Receive Data with Exception interrupt. If REIE is
cleared, the Receive Data with Exception interrupt is disabled. If both REIE and RDRF
are set, and PE, FE, and OR are not all cleared, the SCI requests an SCI Receive Data with
Exception interrupt from the interrupt controller. REIE is cleared by hardware and
software reset.
8.3.2

SCI Status Register (SSR)

The SCI Status Register (SSR) is a 24-bit read-only register used by the DSP to determine
the status of the SCI. The status bits are described in the following paragraphs. When the
SSR is read into the internal data bus, the register contents occupy the low-order byte of
the data bus and all high-order portions are zero-filled.
8.3.2.1

Transmitter Empty (TRNE) SSR Bit 0

The TRNE flag bit is set when both the Transmit Shift Register and Transmit Data
Register (STX) are empty to indicate that there is no data in the transmitter. When TRNE
is set, data written to one of the three STX locations or to the Transmit Data Address
Register (STXA) is transferred to the Transmit Shift Register and is the first data
transmitted. TRNE is cleared when TDRE is cleared by writing data into the STX or the
STXA, or when an idle, preamble, or break is transmitted. This bit, when set, indicates
that the transmitter is empty; therefore, the data written to STX or STXA is transmitted
next. That is, there is no word in the Transmit Shift Register presently being transmitted.
This procedure is useful when initiating the transfer of a message (i.e., a string of
characters). TRNE is set by the hardware, software, SCI individual, and stop reset.
8.3.2.2

Transmit Data Register Empty (TDRE) SSR Bit 1

The TDRE flag bit is set when the SCI Transmit Data Register is empty. When TDRE is
set, new data can be written to one of the SCI Transmit Data Registers (STX) or the
Transmit Data Address Register (STXA). TDRE is cleared when the SCI Transmit Data
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