Real Outputs Only), Decimation By 2 - Motorola DSP56305 User Manual

24-bit digital signal processor
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12.5.5.3
Mode 0 (Complex FIR Filter Generating Real Outputs Only),
Decimation by 2
The following equation is implemented:
Set Up
DSP
Initialization
Processing
MOTOROLA
N 1
FR n ( )
(
HR i ( ) DR n i –
=
i
=
0
• Load Filter Count Register (FCNT) with (number of coefficient
values – 1)
• Choose operation mode (FOM[1:0], FDCM=0, 0, 1) and enable
FCOP (FEN = 1)
Core initializes coefficients in FCM in reverse order, while
imaginary coefficients are first negated, by executing
#filter_count writes to FCIR
• Core or DMA initializes data in FDM in direct order by
executing #filter_count writes to FDIR
Whenever FDIR is empty (FDIBE = 1), the FCOP triggers
core or the DMA to transfer two or four new data words
(one or two complex pairs) to the FDM via FDIR
• Compute F(n) and store result in FDOR
• FCOP triggers core or DMA for output data transfer
• Get new data word
• FCOP increments data memory pointer
• Get new data word
• FCOP increments data memory pointer
DSP56305 User's Manual
(
)
)
(
HI i ( ) DI n i –
Filter Co-Processor
Operation Modes
(
)
)
12-21

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