Motorola DSP56303 Manuals

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Motorola DSP56303 User Manual

Motorola DSP56303 User Manual (320 pages)

24-Bit Digital Signal Processor  
Brand: Motorola | Category: Processor | Size: 4.26 MB
Table of contents
Table Of Contents5................................................................................................................................................................
Manual Organization17................................................................................................................................................................
Manual Conventions18................................................................................................................................................................
High True/low True Signal Conventions18................................................................................................................................................................
Features20................................................................................................................................................................
Dsp56300 Core20................................................................................................................................................................
Dsp56300 Core Functional Blocks21................................................................................................................................................................
Data Alu22................................................................................................................................................................
Data Alu Registers22................................................................................................................................................................
Multiplier-accumulator (mac)22................................................................................................................................................................
Address Generation Unit (agu)23................................................................................................................................................................
Program Control Unit (pcu)23................................................................................................................................................................
Pll And Clock Oscillator24................................................................................................................................................................
Jtag Tap And Once Module25................................................................................................................................................................
On-chip Memory25................................................................................................................................................................
Off-chip Memory Expansion26................................................................................................................................................................
Internal Buses26................................................................................................................................................................
Dsp56303 Block Diagram27................................................................................................................................................................
Peripherals28................................................................................................................................................................
Gpio Functionality28................................................................................................................................................................
Hi0828................................................................................................................................................................
Essi29................................................................................................................................................................
Timer Module30................................................................................................................................................................
Dsp56303 Functional Signal Groupings31................................................................................................................................................................
Signals Identified By Functional Group32................................................................................................................................................................
Power33................................................................................................................................................................
Power Inputs33................................................................................................................................................................
Ground34................................................................................................................................................................
Grounds34................................................................................................................................................................
Clock35................................................................................................................................................................
Phase Lock Loop (pll)35................................................................................................................................................................
Clock Signals35................................................................................................................................................................
Phase Lock Loop Signals35................................................................................................................................................................
External Memory Expansion Port (port A)36................................................................................................................................................................
External Address Bus36................................................................................................................................................................
External Data Bus36................................................................................................................................................................
External Bus Control36................................................................................................................................................................
External Address Bus Signals36................................................................................................................................................................
External Data Bus Signals36................................................................................................................................................................
External Bus Control Signals36................................................................................................................................................................
Interrupt And Mode Control39................................................................................................................................................................
Host Interface (hi08)40................................................................................................................................................................
Host Port Usage Considerations40................................................................................................................................................................
Host Port Configuration41................................................................................................................................................................
Host Interface41................................................................................................................................................................
Enhanced Synchronous Serial Interface 0 (essi0)45................................................................................................................................................................
Enhanced Synchronous Serial Interface 1 (essi1)47................................................................................................................................................................
Serial Communication Interface (sci)49................................................................................................................................................................
Timers50................................................................................................................................................................
Triple Timer Signals50................................................................................................................................................................
Jtag/once Interface51................................................................................................................................................................
Program Memory Space53................................................................................................................................................................
Internal Program Memory54................................................................................................................................................................
Memory Switch Modes—program Memory54................................................................................................................................................................
Instruction Cache54................................................................................................................................................................
Program Bootstrap Rom55................................................................................................................................................................
X Data Memory Space55................................................................................................................................................................
Internal X Data Memory55................................................................................................................................................................
Memory Switch Modes—x Data Memory55................................................................................................................................................................
Internal I/o Space—x Data Memory56................................................................................................................................................................
Y Data Memory Space56................................................................................................................................................................
Internal Y Data Memory56................................................................................................................................................................
Memory Switch Modes—y Data Memory56................................................................................................................................................................
External I/o Space—y Data Memory57................................................................................................................................................................
Dynamic Memory Configuration Switching57................................................................................................................................................................
Sixteen-bit Compatibility Mode Configuration58................................................................................................................................................................
Ram Configuration Summary58................................................................................................................................................................
Dsp56303 Ram Configurations58................................................................................................................................................................
Dsp56303 Ram Address Ranges By Configuration58................................................................................................................................................................
Memory Maps59................................................................................................................................................................
Default Settings (0, 0, 0)59................................................................................................................................................................
Instruction Cache Enabled (0, 0, 1)60................................................................................................................................................................
Switched Program Ram (0, 1, 0)61................................................................................................................................................................
Switched Program Ram And Instruction Cache Enabled (0, 1, 1)62................................................................................................................................................................
Bit Space With Default Ram (1, 0, 0)63................................................................................................................................................................
Bit Space With Instruction Cache Enabled (1, 0, 1)64................................................................................................................................................................
Bit Space With Switched Program Ram (1, 1, 0)65................................................................................................................................................................
Operating Modes68................................................................................................................................................................
Dsp56303 Operating Modes68................................................................................................................................................................
Bootstrap Program74................................................................................................................................................................
Central Processor Unit (cpu) Registers75................................................................................................................................................................
Status Register (sr)75................................................................................................................................................................
Status Register Bit Definitions76................................................................................................................................................................
Operating Mode Register (omr)81................................................................................................................................................................
Operating Mode Register (omr) Bit Definitions81................................................................................................................................................................
Configuring Interrupts84................................................................................................................................................................
Interrupt Priority Registers (iprc And Iprp)85................................................................................................................................................................
Interrupt Priority Register-peripherals (iprp) (x:$fffffe)85................................................................................................................................................................
Interrupt Priority Register-core (iprc) (x:$ffffff)85................................................................................................................................................................
Interrupt Table Memory Map86................................................................................................................................................................
Interrupt Priority Level Bits86................................................................................................................................................................
Interrupt Sources86................................................................................................................................................................
Processing Interrupt Source Priorities Within An Ipl88................................................................................................................................................................
Interrupt Source Priorities Within An Ipl88................................................................................................................................................................
Pll Control Register (pctl)90................................................................................................................................................................
Pll Control Register (pctl) Bit Definitions90................................................................................................................................................................
Bus Interface Unit (biu) Registers91................................................................................................................................................................
Bus Control Register91................................................................................................................................................................
Bus Control Register (bcr)91................................................................................................................................................................
Bus Control Register (bcr) Bit Definitions92................................................................................................................................................................
Dram Control Register (dcr)93................................................................................................................................................................
Dram Control Register (dcr) Bit Definitions94................................................................................................................................................................
Address Attribute Registers (aar[0–3])96................................................................................................................................................................
Address Attribute Registers (aar[0–3]) (x:$fffff9–$fffff6)96................................................................................................................................................................
Address Attribute Registers (aar[0–3]) Bit Definitions96................................................................................................................................................................
Dma Control Registers 5–0 (dcr[5–0])98................................................................................................................................................................
Dma Control Register (dcr)98................................................................................................................................................................
Dma Control Register (dcr) Bit Definitions98................................................................................................................................................................
Device Identification Register (idr)103................................................................................................................................................................
Identification Register Configuration (revision E)103................................................................................................................................................................
Jtag Identification (id) Register104................................................................................................................................................................
Jtag Boundary Scan Register (bsr)104................................................................................................................................................................
Jtag Identification Register Configuration (revision E)104................................................................................................................................................................
Peripheral Initialization Steps105................................................................................................................................................................
Mapping The Control Registers106................................................................................................................................................................
Reading Status Registers106................................................................................................................................................................
Memory Mapping Of Peripherals Control Registers106................................................................................................................................................................
Data Transfer Methods107................................................................................................................................................................
Polling107................................................................................................................................................................
Interrupts107................................................................................................................................................................
Dma-accessible Registers109................................................................................................................................................................
Advantages And Disadvantages110................................................................................................................................................................
General-purpose Input/output (gpio)110................................................................................................................................................................
Port B Signals And Registers111................................................................................................................................................................
Port B Signals111................................................................................................................................................................
Port C Signals And Registers112................................................................................................................................................................
Port D Signals And Registers112................................................................................................................................................................
Port C Signals112................................................................................................................................................................
Port D Signals112................................................................................................................................................................
Port E Signals And Registers113................................................................................................................................................................
Triple Timer Signals And Registers113................................................................................................................................................................
Port E Signals113................................................................................................................................................................
Dsp Core Interface115................................................................................................................................................................
Host Processor Interface116................................................................................................................................................................
Host Port Signals117................................................................................................................................................................
Hi08 Signal Definitions For Operational Modes117................................................................................................................................................................
Overview118................................................................................................................................................................
Hi08 Data Strobe Signals118................................................................................................................................................................
Hi08 Host Request Signals118................................................................................................................................................................
Hi08 Block Diagram119................................................................................................................................................................
Operation120................................................................................................................................................................
Software Polling121................................................................................................................................................................
Core Interrupts And Host Commands121................................................................................................................................................................
Hi08 Core Interrupt Operation122................................................................................................................................................................
Core Dma Access123................................................................................................................................................................
Host Requests123................................................................................................................................................................
Dma Request Sources123................................................................................................................................................................
Hi08 Host Request Structure124................................................................................................................................................................
Hreq Pin Operation In Single Request Mode (icr[2]=hdrq=0)124................................................................................................................................................................
Htrq And Hrrq Pin Operation In Double Request Mode (icr[2]=hdrq=1)124................................................................................................................................................................
Endian Modes125................................................................................................................................................................
Hi08 Read And Write Operations In Little Endian Mode125................................................................................................................................................................
Boot-up Using The Hi08 Host Port126................................................................................................................................................................
Hi08 Read And Write Operations In Big Endian Mode126................................................................................................................................................................
Hi08 Boot Modes126................................................................................................................................................................
Dsp Core Programming Model127................................................................................................................................................................
Host Control Register (hcr)128................................................................................................................................................................
Host Control Register (hcr) (x:$ffffc2)128................................................................................................................................................................
Host Control Register (hcr) Bit Definitions128................................................................................................................................................................
Host Status Register (hsr)129................................................................................................................................................................
Host Status Register (hsr) (x:$ffffc3)129................................................................................................................................................................
Host Status Register (hsr) Bit Definitions129................................................................................................................................................................
Host Data Direction Register (hddr)130................................................................................................................................................................
Host Data Register (hdr)130................................................................................................................................................................
Host Data Direction Register (hddr) (x:$ffffc8)130................................................................................................................................................................
Host Data Register (hdr) (x:$ffffc8)130................................................................................................................................................................
Hdr And Hddr Functionality130................................................................................................................................................................
Host Base Address Register (hbar)131................................................................................................................................................................
Host Base Address Register (hbar) (x:$ffffc5)131................................................................................................................................................................
Self Chip-select Logic131................................................................................................................................................................
Host Base Address Register (hbar) Bit Definitions131................................................................................................................................................................
Host Port Control Register (hpcr)132................................................................................................................................................................
Host Port Control Register (hpcr) (x:$ffffc4)132................................................................................................................................................................
Host Port Control Register (hpcr) Bit Definitions132................................................................................................................................................................
Host Transmit (htx) Register135................................................................................................................................................................
Single-strobe Mode135................................................................................................................................................................
Dual-strobe Mode135................................................................................................................................................................
Host Receive (hrx) Register136................................................................................................................................................................
Dsp-side Registers After Reset136................................................................................................................................................................
Host Programmer Model137................................................................................................................................................................
Interface Control Register (icr)138................................................................................................................................................................
Host-side Register Map138................................................................................................................................................................
Interface Control Register (icr) Bit Definitions139................................................................................................................................................................
Command Vector Register (cvr)140................................................................................................................................................................
Interface Status Register (isr)141................................................................................................................................................................
Command Vector Register (cvr) Bit Definitions141................................................................................................................................................................
Interface Status Register (isr) Bit Definitions142................................................................................................................................................................
Interrupt Vector Register (ivr)143................................................................................................................................................................
Receive Data Registers (rxh:rxm:rxl)144................................................................................................................................................................
Transmit Data Registers (txh:txm:txl)144................................................................................................................................................................
Host-side Registers After Reset145................................................................................................................................................................
Programming Model Quick Reference146................................................................................................................................................................
Hi08 Programming Model, Dsp Side146................................................................................................................................................................
Hi08 Programming Model: Host Side148................................................................................................................................................................
Essi Block Diagram149................................................................................................................................................................
Essi Enhancements150................................................................................................................................................................
Essi Data And Control Signals151................................................................................................................................................................
Serial Transmit Data Signal (std)151................................................................................................................................................................
Serial Receive Data Signal (srd)151................................................................................................................................................................
Serial Clock (sck)151................................................................................................................................................................
Essi Clock Sources151................................................................................................................................................................
Serial Control Signal (sc0)152................................................................................................................................................................
Serial Control Signal (sc1)152................................................................................................................................................................
Mode And Signal Definitions153................................................................................................................................................................
Serial Control Signal (sc2)154................................................................................................................................................................
Essi After Reset154................................................................................................................................................................
Initialization154................................................................................................................................................................
Exceptions155................................................................................................................................................................
Operating Modes: Normal, Network, And On-demand158................................................................................................................................................................
Normal/network/on-demand Mode Selection158................................................................................................................................................................
Synchronous/asynchronous Operating Modes159................................................................................................................................................................
Frame Sync Selection159................................................................................................................................................................
Frame Sync Signal Format159................................................................................................................................................................
Frame Sync Length For Multiple Devices160................................................................................................................................................................
Word Length Frame Sync And Data Word Timing160................................................................................................................................................................
Frame Sync Polarity160................................................................................................................................................................
Byte Format (lsb/msb) For The Transmitter161................................................................................................................................................................
Flags161................................................................................................................................................................
Essi Programming Model162................................................................................................................................................................
Essi Control Register A (cra)162................................................................................................................................................................
Essi Control Register A(cra)162................................................................................................................................................................
Essi Control Register A (cra) Bit Definitions163................................................................................................................................................................
Essi Clock Generator Functional Block Diagram165................................................................................................................................................................
Essi Frame Sync Generator Functional Block Diagram165................................................................................................................................................................
Essi Control Register B (crb)166................................................................................................................................................................
Essi Control Register B (crb) Bit Definitions167................................................................................................................................................................
Crb Fsl0 And Fsl1 Bit Operation (fsr = 0)172................................................................................................................................................................
Crb Syn Bit Operation173................................................................................................................................................................
Normal Mode, External Frame Sync (8 Bit, 1 Word In Frame)175................................................................................................................................................................
Network Mode, External Frame Sync (8 Bit, 2 Words In Frame)175................................................................................................................................................................
Essi Status Register (ssisr)176................................................................................................................................................................
Essi Status Register (ssisr) Bit Definitions176................................................................................................................................................................
Essi Receive Shift Register177................................................................................................................................................................
Essi Receive Data Register (rx)178................................................................................................................................................................
Essi Transmit Shift Registers178................................................................................................................................................................
Essi Data Path Programming Model (shfd = 0)179................................................................................................................................................................
Essi Data Path Programming Model (shfd = 1)180................................................................................................................................................................
Essi Transmit Data Registers (tx[2–0])181................................................................................................................................................................
Essi Time Slot Register (tsr)181................................................................................................................................................................
Transmit Slot Mask Registers (tsma, Tsmb)181................................................................................................................................................................
Essi Transmit Slot Mask Register A (tsma)181................................................................................................................................................................
Essi Transmit Slot Mask Register B (tsmb)182................................................................................................................................................................
Receive Slot Mask Registers (rsma, Rsmb)183................................................................................................................................................................
Essi Receive Slot Mask Register A (rsma)183................................................................................................................................................................
Essi Receive Slot Mask Register B (rsmb)183................................................................................................................................................................
Gpio Signals And Registers184................................................................................................................................................................
Port Control Registers (pcrc And Pcrd)184................................................................................................................................................................
Port Control Registers (pcrc X:$ffffbf) (pcrd X:$fffaf)184................................................................................................................................................................
Port Direction Registers (prrc And Prrd)185................................................................................................................................................................
Port Direction Registers (prrc X:$ffffbe) (prrd X: $ffffae)185................................................................................................................................................................
Essi Port Signal Configurations185................................................................................................................................................................
Port Data Registers (pdrc And Pdrd)186................................................................................................................................................................
Port Data Registers (pdrc X:$ffffbd) (pdrd X: $ffffad)186................................................................................................................................................................
Synchronous Mode188................................................................................................................................................................
Asynchronous Mode188................................................................................................................................................................
Multidrop Mode188................................................................................................................................................................
Transmitting Data And Address Characters189................................................................................................................................................................
Wired-or Mode189................................................................................................................................................................
Idle Line Wakeup189................................................................................................................................................................
Address Mode Wakeup189................................................................................................................................................................
I/o Signals189................................................................................................................................................................
Receive Data (rxd)190................................................................................................................................................................
Transmit Data (txd)190................................................................................................................................................................
Sci Serial Clock (sclk)190................................................................................................................................................................
Sci After Reset191................................................................................................................................................................
Sci Registers After Reset191................................................................................................................................................................
Sci Initialization192................................................................................................................................................................
Preamble, Break, And Data Transmission Priority193................................................................................................................................................................
Bootstrap Loading Through The Sci (boot Mode 2 Or A)194................................................................................................................................................................
Sci Programming Model195................................................................................................................................................................
Sci Data Word Formats (ssftd = 1), 1196................................................................................................................................................................
Sci Data Word Formats (ssftd = 0), 2197................................................................................................................................................................
Sci Control Register (scr)198................................................................................................................................................................
Sci Control Register (scr) Bit Definitions198................................................................................................................................................................
Sci Status Register (ssr)203................................................................................................................................................................
Sci Status Register203................................................................................................................................................................
Sci Status Register (ssr) Bit Definitions203................................................................................................................................................................
Sci Clock Control Register (sccr)205................................................................................................................................................................
Sci Clock Control Register (sccr) Bit Definitions205................................................................................................................................................................
Sci Baud Rate Generator206................................................................................................................................................................
X Serial Clock207................................................................................................................................................................
Sci Data Registers208................................................................................................................................................................
Sci Receive Register (srx)208................................................................................................................................................................
Sci Programming Model—data Registers208................................................................................................................................................................
Sci Transmit Register (stx)209................................................................................................................................................................
Port E Control Register (pcre)210................................................................................................................................................................
Port E Control Register (pcre X:$ffff9f)210................................................................................................................................................................
Port E Direction Register (prre)211................................................................................................................................................................
Port E Data Register (pdre)211................................................................................................................................................................
Port E Direction Register (prre X:$ffff9e)211................................................................................................................................................................
Port Data Registers (pdre X:$ffff9d)211................................................................................................................................................................
Triple Timer Module Block Diagram214................................................................................................................................................................
Individual Timer Block Diagram214................................................................................................................................................................
Timer After Reset215................................................................................................................................................................
Timer Module Block Diagram215................................................................................................................................................................
Timer Initialization216................................................................................................................................................................
Timer Exceptions216................................................................................................................................................................
Triple Timer Modes218................................................................................................................................................................
Timer Gpio (mode 0)218................................................................................................................................................................
Timer Mode (trm = 1)219................................................................................................................................................................
Timer Mode (trm = 0)219................................................................................................................................................................
Timer Pulse (mode 1)220................................................................................................................................................................
Pulse Mode (trm = 1)220................................................................................................................................................................
Pulse Mode (trm = 0)221................................................................................................................................................................
Timer Toggle (mode 2)222................................................................................................................................................................
Toggle Mode, Trm = 1222................................................................................................................................................................
Toggle Mode, Trm = 0223................................................................................................................................................................
Timer Event Counter (mode 3)224................................................................................................................................................................
Event Counter Mode, Trm = 1224................................................................................................................................................................
Event Counter Mode, Trm = 0225................................................................................................................................................................
Signal Measurement Modes226................................................................................................................................................................
Measurement Input Width (mode 4)226................................................................................................................................................................
Pulse Width Measurement Mode, Trm = 1227................................................................................................................................................................
Pulse Width Measurement Mode, Trm = 0227................................................................................................................................................................
Measurement Input Period (mode 5)228................................................................................................................................................................
Period Measurement Mode, Trm = 1228................................................................................................................................................................
Period Measurement Mode, Trm = 0229................................................................................................................................................................
Measurement Capture (mode 6)230................................................................................................................................................................
Capture Measurement Mode, Trm = 0230................................................................................................................................................................
Pulse Width Modulation (pwm, Mode 7)231................................................................................................................................................................
Pulse Width Modulation Toggle Mode, Trm = 1232................................................................................................................................................................
Pulse Width Modulation Toggle Mode, Trm = 0233................................................................................................................................................................
Watchdog Modes234................................................................................................................................................................
Watchdog Pulse (mode 9)234................................................................................................................................................................
Watchdog Pulse Mode235................................................................................................................................................................
Watchdog Toggle (mode 10)236................................................................................................................................................................
Watchdog Toggle Mode236................................................................................................................................................................
Reserved Modes237................................................................................................................................................................
Special Cases237................................................................................................................................................................
Dma Trigger237................................................................................................................................................................
Triple Timer Module Programming Model237................................................................................................................................................................
Prescaler Counter237................................................................................................................................................................
Timer Module Programmer's Model238................................................................................................................................................................
Timer Prescaler Load Register (tplr)239................................................................................................................................................................
Timer Prescaler Load Register (tplr) Bit Definitions239................................................................................................................................................................
Timer Prescaler Count Register (tpcr)240................................................................................................................................................................
Timer Control/status Register (tcsr)240................................................................................................................................................................
Timer Prescaler Count Register (tpcr) Bit Definitions240................................................................................................................................................................
Timer Control/status Register (tcsr) Bit Definitions240................................................................................................................................................................
Inverter (inv) Bit Operation244................................................................................................................................................................
Timer Load Register (tlr)245................................................................................................................................................................
Timer Compare Register (tcpr)246................................................................................................................................................................
Timer Count Register (tcr)246................................................................................................................................................................
A.1 Bootstrap Code247................................................................................................................................................................
A.2 Equates For I/o Port Programming254................................................................................................................................................................
A.3 Host Interface (hi08) Equates255................................................................................................................................................................
A.4 Serial Communications Interface (sci) Equates256................................................................................................................................................................
A.5 Enhanced Synchronous Serial Interface (essi) Equates257................................................................................................................................................................
A.6 Exception Processing Equates259................................................................................................................................................................
A.7 Timer Module Equates260................................................................................................................................................................
A.8 Direct Memory Access (dma) Equates261................................................................................................................................................................
A.9 Phase Locked Loop (pll) Equates263................................................................................................................................................................
A.10 Bus Interface Unit (biu) Equates264................................................................................................................................................................
A.11 Interrupt Equates266................................................................................................................................................................
B-1 Guide To Programming Sheets270................................................................................................................................................................
B.1 Internal I/o Memory Map271................................................................................................................................................................
B-2 Internal I/o Memory Map (x Data Memory)271................................................................................................................................................................
B.2 Interrupt Sources And Priorities276................................................................................................................................................................
B-3 Interrupt Sources276................................................................................................................................................................
B-4 Interrupt Source Priorities Within An Ipl278................................................................................................................................................................
B.3 Programming Sheets280................................................................................................................................................................
B-1 Status Register (sr)280................................................................................................................................................................
B-2 Operating Mode Register (omr)281................................................................................................................................................................
B-3 Interrupt Priority Register-core (iprc)282................................................................................................................................................................
B-4 Interrupt Priority Register-peripherals (iprp)283................................................................................................................................................................
B-5 Phase-locked Loop Control Register (pctl)284................................................................................................................................................................
B-6 Bus Control Register (bcr)285................................................................................................................................................................
B-7 Dram Control Register (dcr)286................................................................................................................................................................
B-8 Address Attribute Registers (aar[3–0])287................................................................................................................................................................
B-9 Dma Control Registers 5–0 (dcr[5–0])288................................................................................................................................................................
B-10 Host Transmit Data Register289................................................................................................................................................................
B-11 Host Base Address And Host Port Control Registers290................................................................................................................................................................
B-12 Host Control Register291................................................................................................................................................................
B-13 Interrupt Control And Command Vector Registers292................................................................................................................................................................
B-14 Interrupt Vector And Host Transmit Data Registers293................................................................................................................................................................
B-15 Essi Control Register A (cra)294................................................................................................................................................................
B-16 Essi Control Register B (crb)295................................................................................................................................................................
B-17 Essi Transmit And Receive Slot Mask Registers (tsm, Rsm)296................................................................................................................................................................
B-18 Sci Control Register (scr)297................................................................................................................................................................
B-19 Sci Clock Control Registers (sccr)298................................................................................................................................................................
B-20 Timer Prescaler Load Register (tplr)299................................................................................................................................................................
B-21 Timer Control/status Register (tcsr)300................................................................................................................................................................
B-22 Timer Load Registers (tlr)301................................................................................................................................................................
B-23 Host Data Direction And Host Data Registers (hddr, Hdr)302................................................................................................................................................................
B-24 Port C Registers (pcrc, Prrc, Pdrc)303................................................................................................................................................................
B-25 Port D Registers (pcrd, Prrd, Pdrd)304................................................................................................................................................................
B-26 Port E Registers (pcre, Prre, Pdre)305................................................................................................................................................................

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