Peripheral Module Bus (Pmb) Interface; Figure 12-1 Filter Co-Processor Block Diagram - Motorola DSP56305 User Manual

DMA BUS
PMB
GDB BUS
Interface
FDIR
Control
Logic
12.3.1

Peripheral Module Bus (PMB) Interface

The Peripheral Module Bus (PMB) interface block provides the control and status
registers, buffers the internal bus from the coprocessor, decodes addresses, and
generates and controls the handshake signals required for DMA and interrupt
operations. The block generates the interrupt and DMA trigger signals, whenever data
transfer is required.
The control and status registers in the PMB are described in detail in the programming
model (see Section 12.4). The interface registers are accessible to the DSP56300 core
through the PMB.
MOTOROLA
4-Word
Data Input Buffer
FDM
Data
Memory Bank
84 × 16-bit
Rounding & Limiting

Figure 12-1 Filter Co-Processor Block Diagram

DSP56305 User's Manual
FCNT 1-Word Coefficient
Filter Count
Address
Generator
Memory Bank
FMAC
16 × 16 → 40-bit
FDOR
Output Buffer
Filter Co-Processor
Block Description
FCIR
Input Buffer
FCM
Coefficients
42 × 16-bit
AA1118
12-5