Table 13-8 Interrupt And Dma Sources; Table 13-9 I/O Register Usage; I/O Register And Related Interrupts For Different Modes - Motorola DSP56305 User Manual

13.6.2 Interrupt and DMA Sources
Interrupt
Source
DREQ
DOBF Viterbi Output Buffer Full
DRDY Viterbi Data Out Request
DONE
OPC Viterbi Operation Complete
13.6.3

I/O Register and Related Interrupts for Different Modes

Operation
Input
Mode
Equalization VDR
Decoding
VDR
Encoding VDR
Note: 1. A sequential write of all symbol-bits to VDR-FIFO is required for each request.
MOTOROLA

Table 13-8 Interrupt and DMA Sources

Interrupt Vector
Viterbi Data In Request
Viterbi Processing Done

Table 13-9 I/O Register Usage

Interrupt
Output
Enable Bit
DIIE
VDOR DOIE
1 DIIE
VDOR DOIE
DIIE
VDOR DOIE
DSP56305 User's Manual
VITERBI CO-PROCESSOR
Interrupt Vector Address
BASE + $0
BASE + $2
BASE + $4
BASE + $6
BASE + $8
Status Bit Register Content
DREQ 16-bit MF Value
DRDY
DREQ Symbol-Bit, Soft Value
DRDY Hard Decoded Value
DREQ Hard Input to Encoder
DRDY Symbol-Bit Output
Chip Description
DMA
Request
Availability
Yes
Yes
Yes
Yes
No
Hard Data
13-31