Master Transaction Termination (Mtt) Bit 15; System Error Force (Serf) Bit 16 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.2.9

Master Transaction Termination (MTT) Bit 15

The MTT bit is used for the generation of a PCI master initiated transaction termination.
When the HI32, in the PCI mode (HM=$1), is the active PCI master, if MTT is set, by the
DSP56300 core, a master initiated transaction termination (not master-abort) is
generated. MTT is cleared by the HI32 hardware when the PCI bus is in the idle state.
MTT cannot be written zero by the DSP56300 core. This bit is used to end an unlimited
length burst.
MTT is ignored when the HI32 is not in the PCI mode (HM≠$1).
Hardware and software resets clear MTT.
6.5.2.10

System Error Force (SERF) Bit 16

The SERF bit controls HSERR signal state in the PCI mode (HM=$1). When SERF is set
by the DSP56300 core and the HI32 is the current PCI bus master or a selected target, the
HSERR signal is pulsed one PCI clock cycle, if the system error enable (SERE) bit is set in
the status/command configuration register (CSTR/CCMR); the signalled system error
(SSE) bit is set in the CSTR/CCMR. SERF is cleared by the HI32 hardware after HSERR is
asserted. If SERF is cleared, the HSERR signal is controlled by the HI32 hardware (see
HSERR signal definition in Table 6-5). SERF cannot be written zero by the DSP56300
core.
SERF is ignored when the SERE bit is cleared or when the HI32 is not an active PCI agent
(i.e. HM≠$1 or the HI32 is not the current PCI bus master or a selected target).
Hardware and software resets clear SERF.
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