Timer Event Counter (Mode 3) - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Modes of Operation
9.4.1.4

Timer Event Counter (Mode 3)

Bit Settings
TC3 TC2 TC1
0 0 1
In this mode, the timer counts external events and issues an interrupt when a preset
number of events is counted.
Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count
value into the TCPR. The counter is loaded with the TLR value when the first timer clock
signal is received. The timer clock signal can be taken from either the TIO input signal or
the prescaler clock output. Each subsequent clock signal increments the counter. If an
external clock is used, it must be internally synchronized to the internal clock and its
frequency must be less than the DSP56305 internal operating frequency divided by four
(i.e., CLK/4).
The value of the INV bit (TCSR Bit 8) determines whether low-to-high (0 to 1) transitions
or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low
transitions increment the counter. If the INV bit is cleared, low-to-high transitions
increment the counter.
When the counter matches the TCPR value, the TCF bit (TCSR Bit 21) is set, if the TCIE
bit (TCSR Bit 2) is set, a compare interrupt is generated. If the TRM bit (TCSR Bit 9) is set,
the counter is loaded with the TLR value on the next timer clock signal and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer clock signal.
This process is repeated until the timer is disabled (i.e., until the TE bit is cleared). If the
counter overflows, the TOF bit (TCSR Bit 20) is set, and if the TOIE bit (TCSR Bit 1) is set,
an overflow interrupt is generated. The counter contents can be read at any time by
reading the TCR.
9-22
TC0 TIO Clock
1 Input External
DSP56305 User's Manual
Mode Characteristics
# KIND
3 Timer
NAME
Event Counter
MOTOROLA