Programming Considerations; Input Phase; Run Phase - Motorola DSP56305 User Manual

stages (maximum degree of 48) can be generated. The Zero Detect function is signaled if
the bits defined in the Bit Select register (CBSRz) of both CFSRs are zero. The feedback
line to both CFSRs is driven by the bit selected by the Mask register (CMSKA) of CFSRA.
This mode is suitable for encoding and decoding of Fire codes with long burst error
correction capability.
14.6

PROGRAMMING CONSIDERATIONS

The processing session consists of three phases: input phase, run phase, and output
phase, driven by the Input Counter, Run Counter, and Output Counter, respectively.
14.6.1

Input Phase

The input phase takes an input data bit coming from the pre-loaded data FIFO register
(CDFR) and shifts it into the enabled CFSRs (according to INE[3:0] bits in CSFTB and
OPM[1:0] bits in CCSR). Following every bit shift the Input Counter is decremented. The
input phase is entered if the Input Counter is non-zero or if CM is set. When in the input
phase, the stepping function and the output data bits are disabled. The input phase
terminates when the Input Counter reaches zero provided that CM bit in CCNT is
cleared.
14.6.2

Run Phase

The run phase starts immediately after the input phase completes, if the Run Counter is
non-zero. In the run phase, data input is disabled and the CFSRs (enabled according to
the OPM[1:0] bits in CCSR) are shifted without any new data being input. Every shift
causes the Run Counter to be decremented.
In the Cipher modes (OPM1 = 0), the stepping function is enabled during the run and
output phases, that is, CFSRs can selectively be disabled from shifting according to the
contents of the Step Function Table. In the Parity Coding modes (OPM1 = 1) shifts are
always enabled.
Data output is disabled during the run phase. Usually the run phase terminates when
the Run Counter reaches zero. However, the run phase may terminate earlier, if the
CCOP operates in Parity Mode (OPM1 = 1) and HOZD is set. In this condition the Zero
Detect function is enabled on selected bits, and when zero is detected the run phase is
terminated and the Run Counter is frozen. It is therefore possible for a run phase to be
MOTOROLA DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
Programming Considerations
14-23