Table 12-3 Fcop Register Read/Write Handling; Fcop Data Input Register (Fdir); Fcop Data Output Register (Fdor) - Motorola DSP56305 User Manual

Filter Co-Processor
Programming Model
Reads and writes of data and non-data are treated differently, as detailed below in Table
12-3.

Table 12-3 FCOP Register Read/Write Handling

Data
• When a data source (FDOR) is read to a 24-bit destination (bus, register,
Transfers
• When a 24-bit source (bus, register, memory, etc.) is written to a data
Non-Data
• When a non-data register (FCNT or FCSR) is read to a 24-bit destination
Transfers
• When a 24-bit source (bus, register, memory, etc.) is written to a
12.4.2

FCOP Data Input Register (FDIR)

The FCOP Data Input Register (FDIR) is a 4-word deep 16-bit wide FIFO used for
DSP-to-FCOP data transfers. Up to four data samples can be written into FDIR using the
same address. Data from FDIR is transferred to the FCOP Data Memory bank (FDM) for
filter processing. For proper operation, data should be written to FDIR only if the FDIBE
status bit is set, indicating that the FIFO is empty. Writing to FDIR clears FDIBE. The
user may use interrupt requests or DMA requests to trigger the DSP56300 core for data
transfers. FDIR can be written by the DSP56300 core and DMA. FDIR is also referred to
as the FCOP Data Input Buffer.
12.4.3

FCOP Data Output Register (FDOR)

The FCOP Data Output Register (FDOR) is a 16-bit wide, read-only register used for
FCOP-to-DSP data transfers. Data is transferred from the FMAC to FDOR after
processing of all filter taps is completed for a specific set of input samples, that is, after
filter processing has been completed. For proper operation, data should be read from
FDOR only if the FDOBF status bit is set, indicating that FDOR contains data. The user
may use interrupt or DMA requests to trigger the DSP56300 core for data transfers.
FDOR can be read by the DSP56300 core and DMA. FDOR is also referred to as the FCOP
Data Output Buffer.
12-8
memory, etc.), the 16-bit data value occupies the 16 Most Significant Bits
(MSBs) of the 24-bit destination and the 8 Least Significant Bits (LSBs)
are zeroed.
destination (FDIR or FCIR), the 16 MSBs of the 24-bit source will be
written to the 16-bit destination.
(bus, register, memory, etc.), the 16-bit value will be zero extended to a
24-bit value.
non-data register, the 8 MSBs must be written with zero for future
compatibility.
DSP56305 User's Manual MOTOROLA