Motorola DSP56305 User Manual page 550

CYCLIC CODE CO-PROCESSOR
Configuration Examples
Two programming cases are considered:
Bit #23 of
CFSRA if n≤24
+
Bit #23 of
CFSRB if n≤48
m
0
D(x)
Input Data
Circuit for multiplying D(x) by M(x) = m
and dividing the product by G(x) = 1+g
14.7.1.1 Case 1 - Polynomials of degree n
In this case the Parity Coding mode using one CFSR is used (OPM[1:0] = 10 in CCSR),
that is, only CFSRA is configured. Since the data sequence is input from the left side,
LRC is cleared. The values of the coefficients g
significant bit) of CFBTA and CFFTA, respectively. Similarly, g
bit 22 of CFBTA and CFFTA, respectively. The other coefficients (g
into bit (24–a) of CFBTA and CFFTA, respectively. The polynomial degree, n, is input by
setting bit (24–n) of CMSKA while all other bits are cleared. The parameter, m
into INE0. If m = 1, INE0 = 1, and if m
0
feedforward path is always enabled and not affected by the INE0 bit.
14.7.1.2 Case 2 - Polynomials of degree n, such that 25
In this case the Parity Coding mode using two concatenated CFSRs is used (OPM[1:0] =
11 in CCSR), that is, CFSRB and CFSRA are concatenated together to form one
double-length CFSR. Since the data sequence is input from the left side, the LRC bit in
CCSR is cleared. The values of the coefficients g
significant bit) of CFBTB and CFFTB, respectively. Similarly, g
22 of CFBTB and CFFTB, respectively, and so on. The twenty- fourth coefficients, g
m , are input into bit 0 (the least significant bit) of CFBTB and CFFTB, respectively. The
24
twenty-fifth coefficients, g
14-28
g
1
Bit #22 of
CFSRA if n≤24
+
Bit #22 of
CFSRB if n≤48
m
1
Figure 14-9 Shortened Cyclic Code Circuit
= 0, INE0 = 0. Notice that the input data to the
0
and m , are input into bit 23 (the most significant bit) of
25 25
DSP56305 User's Manual
g g
G(x)
2 n–2
+ +
m m
M(x)
2 n–2
2
+m •x+m •x +...+m
0 1 2
2
•x+g •x +...+g
1 2 n–1
≤
24
and m are input into bit 23 (the most
1 1
and m are input into bit 23 (the most
1 1
2
g
n–1
Bit #(25-n) of
CFSRA if n≤24
+
Bit #(49-n) of
CFSRA if n≤48
m
n–1
n–1
•x
n–1
n–1 n
•x +x
and m are input into
2 2
and m ) are input
a a
, is input
0
≤ ≤
n 48
and m are input into bit
2
24
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AA1308
and