Motorola DSP56305 User Manual page 656

R
Prescale Modulus Select bits (PM0–PM7) 7-15
Prescaler Clock Enable bit (PCE) 9-16
Prescaler Counter 9-5
Prescaler Counter Value bits (PC0-PC20) 9-7
Prescaler Load Value bits (PL0-PL20) 9-6
Prescaler Range bit (PSR) 7-15
Prescaler Source bits (PL21-PL22) 9-6
Program Address Bus (PAB) 1-13
Program Address Generator (PAG) 1-10
Program Control Unit (PCU) 1-10
Program Counter register (PC) 1-10
Program Data Bus (PDB) 1-13
Program Decode Controller (PDC) 1-10
Program Interrupt Controller (PIC) 1-10
Program Memory Expansion Bus 1-13
program RAM 3-4
Programming Sheets — See Appendix B
PRRC register 7-55
PRRD register 7-55
PRRE register 8-30
PSR bit 7-15
R
R/W bit 10-6
R8 bit 8-16
RCM bit 8-19
RDF bit 7-37
RDRF bit 8-15
,
RE bit 7-33 8-11
Read/Write Command bit (R/W) 10-6
Receive Clock Mode Source bit (RCM) 8-19
Receive Data Register (RX) 7-40
Receive Data Register Full bit (RDF) 7-37
Receive Data Register Full bit (RDRF) 8-15
Receive Data signal (RXD) 8-4
Receive Exception Interrupt Enable bit (REIE) 7-35
Receive Frame Sync Flag bit (RFS) 7-36
Receive Interrupt Enable bit (RIE) 7-34
Receive Last Slot Interrupt Enable bit (RLIE) 7-34
Receive Shift Register 7-40
Receive Slot Mask Registers (RSMA, RSMB) 7-42
Received Bit 8 Address bit (R8) 8-16
Receiver Enable bit (RE) 8-11
Receiver Overrun Error Flag bit (ROE) 7-37
Receiver Wakeup Enable bit (SBK) 8-11
Register Select bits (RS0–RS4) 10-6
,
REIE bit 7-35 8-14
reserved bits
Index-6
RESET 2-16
reverse-carry adder 1-9
RFS bit 7-36
RIE bit 7-34
RLIE bit 7-34
ROE bit 7-37
ROM
RS0–RS4 bits 10-6
RSMA, RSMB registers 7-42
RW00–RW01 bits 10-12
RW10–RW11 bits 10-13
RWU bit 8-11
RX register 7-40
RXD signal 8-4
S
SAMPLE/PRELOAD instruction 11-9
SBK bit 8-10
SC register 1-11
SC0 signal 7-8
SC1 signal 7-10
SCCR register 8-17
,
8-13
SCD0 bit 7-21
SCD1 bit 7-22
SCD2 bit 7-22
SCI 1-17
DSP56305 User's Manual
,
in CRA register 7-15 7-18
in OBCR register
bits 12–15 10-15
in OSCR register
bit 5, bits 8–23 10-9
in TCSR register
bits 3, 10, 14, 16–19, 22, 23 9-16
in TPCR 9-7
in TPLR 9-6
,
8-13
bootstrap 3-4
,
7-12
bits 0–11—Clock Divider bits
(CD0–CD11) 8-18
bit 12—Clock Out Divider bit (COD) 8-18
bit 13—SCI Clock Prescaler bit (SCP) 8-18
bit 14—Receive Clock Mode Source bit
(RCM) 8-19
bit 15—Transmit Clock Source bit (TCM) 8-20
, ,
2-4 2-35
exceptions 8-29
Idle Line 8-29
Receive Data 8-29
Receive Data with Exception Status 8-29
Timer 8-29
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7-19
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