Pci Master Receive Data Request (Mrrq) Bit 2; Master Address Request (Marq) Bit 4; Address Parity Error (Aper) Bit 5 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.6.3

PCI Master Receive Data Request (MRRQ) Bit 2

The MRRQ bit indicates that the DSP receive data FIFO (DRXR) contains data read from
the host bus by the HI32 master. When the HI32, as master, reads data from the host bus
to the host-to-DSP FIFO (HTXR-DRXR), MRRQ is set. MRRQ is cleared if the DRXR is
emptied by DSP56300 core reads; or the data to be read from the DRXR is slave data.
If MRRQ is set
• if MRIE is set, a master receive data interrupt request is generated
• if enabled by an DSP56300 core DMA channel, a master receive data DMA
request will be generated.
Hardware, software and personal software resets clear MRRQ.
6.5.6.4

Master Address Request (MARQ) Bit 4

The MARQ bit indicates that the HI32 is currently not the initiator of a PCI transaction
and the DPAR can be written with the address of the next transaction. When the HI32
with the PCI bus master enable bit (BM) set in the CCMR, is first programmed to the PCI
mode (HM=$1) or completes a PCI transaction as a master, MARQ is set and, if MAIE is
set, a master address interrupt request is generated. MARQ is cleared by any of the
following:
• the DSP56300 core writes the DPAR
• the PCI bus master enable bit (BM) is cleared in the CCMR
Hardware, software, personal hardware and personal software resets clear MARQ.
6.5.6.5

Address Parity Error (APER) Bit 5

The APER bit indicates that an address parity error has been detected by the HI32
hardware, when in the PCI mode (HM=$1) and the HI32 is a PCI target. At the end of a
transaction, if an address parity error has been detected, APER is set and, if PEIE is set, a
parity error interrupt request is generated.
If an address parity error has been detected:
• the HI32 target claims the cycles and terminates as though the address was
correct.
• if the system error enable (SERE) bit in the status/command configuration
register (CSTR/CCMR) is set, the HSERR signal is pulsed one PCI clock cycle,
and the signalled system error (SSE) bit is set in the CSTR/CCMR.
• the detected parity error bit (DPE) in the CSTR is set.
APER is cleared when it is written one by the DSP56300 core.
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