Motorola DSP56305 User Manual page 655

OnCE PAB Register for Fetch Register
(OPABFR) 10-20
OnCE PIL Register (OPILR) 10-19
OnCE Program Data Bus Register (OPDBR) 10-19
OnCE Status and Control Register (OSCR) 10-8
OnCE Trace Counter (OTC) 10-16
OnCE/JTAG 2-4
OnCE/JTAG port 2-3
On-Chip Emulation (OnCE) module 1-12
On-Chip Emulation module 10-3
on-chip memory 1-12
program 3-4
X data RAM 3-5
Y data RAM 3-6
OPABDR register 10-20
OPABEX register 10-21
OPABFR register 10-20
OPDBR register 10-19
Operating 4-3
operating mode 4-3
bootstrap from byte-wide external memory 4-8
bootstrap through SCI 4-8
,
ESSI 7-43 7-48
expanded 4-6
expanded mode 4-8
Operating Mode Register (OMR) 1-11
operating modes 4-3
OPILR register 10-19
OR bit 8-15
OS0–OS1 bits 10-9
OSCR register 10-8
bit 0—Trace Mode Enable bit (TME) 10-8
bit 1—Interrupt Mode Enable bit (IME) 10-8
bit 2—Software Debug Occurrence bit
(SWO) 10-9
bit 3—Memory Breakpoint Occurrence bit
(MBO) 10-9
bit 4—Trace Occurrence bit (TO) 10-9
bit 5—reserved bit 10-9
bits 6–7—Core Status bits (OS0–OS1) 10-9
reserved bits—bits 8–23 10-10
OTC counter 10-16
Overrun Error Flag bit (OR) 8-15
P
PAB 1-13
PAG 1-10
Parity Error bit (PE) 8-16
Patch Mode
PEN bit 4-23
MOTOROLA
PC register 1-10
PC0-PC20 bits 9-7
PCE bit 9-16
PCRC register 7-54
PCRD register 7-54
PCRE register 8-29
PCTL register
PCU 1-10
PD bits 4-24
PDB 1-13
PDC 1-10
PDRC register 7-56
PDRD register 7-56
PDRE register 8-31
PE bit 8-16
Peripheral I/O Expansion Bus 1-13
PIC 1-10
pin configuration, SCKn 7-6
pin configuration, SCn0 7-8
pin configuration, SCn1 7-11
pin configuration, SCn2 7-8
PL0-PL20 bits 9-6
PL21-PL22 bits 9-6
PLL 1-11
PM0–PM7 bits 7-15
Port A 2-9
Port B 5-3
Port C 2-4
Port C Control Register (PCRC) 7-54
Port C Data Register (PDRC) 7-56
Port C Direction Register (PRRC) 7-55
Port D 2-4
Port D Control Register (PCRD) 7-54
Port D Data Register (PDRD) 7-56
Port D Direction Register (PRRD) 7-55
Port E 2-35
Port E Control Register (PCRE) 8-29
Port E Data Register (PDRE) 8-31
Port E Direction Register (PRRE) 8-30
Power 2-6
power
PreDivider Factor bits (PD) 4-24
DSP56305 User's Manual
bits 0–11—Multiplication Factor bits
(MF0–MF11) 4-23
bit 16—XTAL Disable bit (XTLD) 4-24
bits 20–23—PreDivider Factor bits
(PD0–PD3) 4-24
,
2-8
GPIO 2-5
, ,
2-29 5-3
, ,
2-32 5-4
,
5-4
low 1-7
management 1-7
standby modes 1-7
P
,
7-12
Index-5