Motorola DSP56305 User Manual page 649

HI32 Registers - Quick Reference (Sheet 7 of 8)
Reg Bit #
Mnemonic Name
CCMR 1 MSE Memory Space Enable
CSTR
2 BM Bus Master Enable
6 PERR Parity Error Response
7 WCC Wait Cycle Control
8 SERE System Error Enable
23 FBBC Fast Back-to-Back Capable 1
24 DPR Data Parity Reported
26- DST1-DST0 DEVSEL Timing
25
27 STA Signaled Target Abort
28 RTA Received Target Abort
29 RMA Received Master Abort
30 SSE Signaled System Error
31 DPE Detected Parity Error
CRID 7- RID7-RID0 Revision ID
CCCR 0
15- PI7-PI0 PCI Device Program
8 Interface
23- SC7-SC0 PCI Device Sub-Class
16
31- BC7-BC0 PCI Device Base Class
24
MOTOROLA
Val Function
0 memory space response is
1 disabled
memory space response is
enabled
0 HI32 PCI bus master disabled
1 HI32 PCI bus master enabled
0 HI32 does not drive HPERR
1 HI32 drives HPERR if a parity
error is detected
0 HI32 never executes address
stepping
0 HI32 does not drive HSERR
1 HI32 may drive HSERR
HI32 supports fast
back-to-back transactions as a
target
0 no parity error detected
1 HI32 master parity error
detected or HPERR asserted
01 medium DEVSEL timing
0 HI32 has not generated a
1 target-abort event
HI32 target, generated a
target-abort event
0 HI32 has not received a
1 target-abort event
HI32 master, received a
target-abort event
0 HI32 has not received a
1 master-abort event
HI32 master, terminates a
transaction with master-abort
0 HI32 not asserted HSERR
1 HI32 asserted HSERR
0 no parity error detected
1 parity error detected
DSP56305 User's Manual
PROGRAMMING REFERENCE
Comments
hardwired 0
hardwired 1
cleared by
writing 1
hardwired 01 -
cleared by
writing 1
cleared by
writing 1
cleared by
writing 1
cleared by
writing 1
cleared by
writing 1
via programm
able
(Section
6.10)
Reset Type
HS PH PS
- 0 -
- 0 -
- 0 -
- - -
- 0 -
- - -
- 0 -
- -
- 0 -
- 0 -
- 0 -
- 0 -
- 0 -
- - -
- - -
- - -
- - -
D-49